Skip to content
View LiPtP0000's full-sized avatar
1 follower · 4 following

Achievements

Achievement: YOLOAchievement: Pull SharkAchievement: Quickdraw

Achievements

Achievement: YOLOAchievement: Pull SharkAchievement: Quickdraw

Highlights

  • Pro

Organizations

@autohdw

Block or report LiPtP0000

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. CPU_Design CPU_Design Public

    16-bit single-cycle CPU using Verilog

    TeX

  2. sdr-psk-fpga-2025 sdr-psk-fpga-2025 Public

    Forked from Teddy-van-Jerry/sdr-psk-fpga

    Dual-Mode PSK Transceiver on SDR With FPGA

    Verilog