Hybrid CPU architecture simulation (P-core vs E-core)

[AveryClapp]

Feature Description

Model heterogeneous CPUs with different core types (Intel Alder Lake, ARM big.LITTLE).

Architecture

Intel 12th Gen (Alder Lake)
┌──────────────┐  ┌──────────────┐
│  P-Cores     │  │  E-Cores     │
│  (8 cores)   │  │  (8 cores)   │
│  L1: 48KB    │  │  L1: 32KB    │
│  L2: 1.25MB  │  │  L2: 2MB     │
└──────────────┘  └──────────────┘
        └────────────┬────────────┘
                     ↓
              Shared L3: 30MB

Simulation

• Per-core-type cache configuration
• Thread scheduler (assign threads to P/E cores)
• Power modeling (P-cores higher perf, E-cores lower power)
• Report per-core-type statistics

Challenges

• Need scheduler heuristics (latency-sensitive → P, throughput → E)
• OS thread migration not visible in trace

Config Example

{
  "pCores": { "count": 8, "l1": "48KB", "l2": "1.25MB" },
  "eCores": { "count": 8, "l1": "32KB", "l2": "2MB" },
  "sharedL3": "30MB"
}

Files

• backend/cache-simulator/include/HybridCoreConfig.hpp (new)
• Add --hybrid flag to CLI