pyVhG

A Python based VHDL app to improve productivity of VHDL designs

Table of Contents

1. Application
2. Input YAML specification
3. Prerequisites
4. Use Model
5. Support
6. Roadmap

Application

Goal of this app is to help VHDL designers to quickly adopt modern verification technologies. Benefits include:

• Coverage Driven Verification
• Structured logging
• Reusable, Layered testbench components
• Separate testcases from testbench etc.

It is developed in Python. Currently it supports the popular OSVVM styled testbenches. If you need a variant such as VUnit, UVVM etc. drop us a note, we will consider depending on customer interests and bandwidth.

Input YAML specification

We use YAML file to specify the DUT interface. More details can be found at:

YAML for VHDL Design interface specification

Given a YAML file as input, this app generates necessary files to simulate a given DUT.

Prerequisites

Python 3.x Modelsim - 2020.1 or later OSVVM recent release

Use Model

To run a simple demo, do the following steps:

1. cd examples
2. cd up_down_counter
3. python3 ../../py_src/af_pyvhg_osvvm.py -y dut_src/af_up_dn_counter.yml

This should create a bunch of TB files and a sim_dir to run simulations.

For any new design, please create a YAML file as shown in this example: dut_src/af_up_dn_counter.yml

Once the step-3 above is done, follow the steps shown in README file generated by the app. Quick steps:

4. cd sim_dir
5. make mti

Support

This is an ongoing development project with active features being added. Feel free to open a GitHub issue if you need new features, bug reports etc. Thanks!

Roadmap

1. Support for generics
2. Functional coverage
3. Other EDA tools support