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15 changes: 9 additions & 6 deletions neon_intrinsics/advsimd.rst
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
.. |copyright-date| replace:: 2014-2021
.. |release| replace:: 2021Q2
.. |date-of-issue| replace:: 02 July 2021
.. |release| replace:: development version based on 2021Q2
.. |date-of-issue| replace:: TBD
.. |footer| replace:: Copyright © |copyright-date|, Arm Limited and its
affiliates. All rights reserved.

Expand Down Expand Up @@ -141,12 +141,16 @@ Document history
+------------+-------------------------+-------------------------+
|F |30 May 2020 |Version ACLE Q2 2020 |
+------------+-------------------------+-------------------------+
|G |30 October 2020 |Version ACLE Q2 2020 |
|G |30 October 2020 |Version ACLE Q3 2020 |
+------------+-------------------------+-------------------------+
|H | |date-of-issue| | |release| |
|H |02 July 2021 | 2021Q2 |
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Outdated
+------------+-------------------------+-------------------------+


Changes between next release and 2021Q2
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Fixed the guard macro for the base intrinsics.
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fpetrogalli marked this conversation as resolved.

List of Intrinsics
##################

Expand All @@ -155,7 +159,7 @@ List of Intrinsics
Basic intrinsics
================

The intrinsics in this section are guarded by the macro ``__ARM_FEATURE_SVE``.
The intrinsics in this section are guarded by the macro ``__ARM_NEON``.

Vector arithmetic
~~~~~~~~~~~~~~~~~
Expand Down Expand Up @@ -27488,4 +27492,3 @@ Vector multiply-accumulate by scalar
| bfloat16x8_t b, | 0 <= lane <= 7 | | | |
| const int lane) | | | | |
+--------------------------------------+------------------------+------------------------------------+---------------------+---------------------------+

13 changes: 8 additions & 5 deletions neon_intrinsics/advsimd.template.rst
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
.. |copyright-date| replace:: 2014-2021
.. |release| replace:: 2021Q2
.. |date-of-issue| replace:: 02 July 2021
.. |release| replace:: development version based on 2021Q2
.. |date-of-issue| replace:: TBD
.. |footer| replace:: Copyright © |copyright-date|, Arm Limited and its
affiliates. All rights reserved.

Expand Down Expand Up @@ -141,14 +141,17 @@ Document history
+------------+-------------------------+-------------------------+
|F |30 May 2020 |Version ACLE Q2 2020 |
+------------+-------------------------+-------------------------+
|G |30 October 2020 |Version ACLE Q2 2020 |
|G |30 October 2020 |Version ACLE Q3 2020 |
+------------+-------------------------+-------------------------+
|H | |date-of-issue| | |release| |
|H |02 July 2021 | 2021Q2 |
+------------+-------------------------+-------------------------+


Changes between next release and 2021Q2
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Fixed the guard macro for the base intrinsics.

List of Intrinsics
##################

{intrinsic_table}

2 changes: 1 addition & 1 deletion tools/intrinsic_db/advsimd.csv
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Expand Up @@ -13,7 +13,7 @@
<COMMENT> See the License for the specific language governing permissions and
<COMMENT> limitations under the License.
<HEADER> Intrinsic Argument preparation AArch64 Instruction Result Supported architectures
<SECTION> Basic intrinsics The intrinsics in this section are guarded by the macro ``__ARM_FEATURE_SVE``.
<SECTION> Basic intrinsics The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
int8x8_t vadd_s8(int8x8_t a, int8x8_t b) a -> Vn.8B;b -> Vm.8B ADD Vd.8B,Vn.8B,Vm.8B Vd.8B -> result v7/A32/A64
int8x16_t vaddq_s8(int8x16_t a, int8x16_t b) a -> Vn.16B;b -> Vm.16B ADD Vd.16B,Vn.16B,Vm.16B Vd.16B -> result v7/A32/A64
int16x4_t vadd_s16(int16x4_t a, int16x4_t b) a -> Vn.4H;b -> Vm.4H ADD Vd.4H,Vn.4H,Vm.4H Vd.4H -> result v7/A32/A64
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