Pin llama.cpp bd5b297: HRX remainder prefill, 32K+ prompts, mixed-format SwiGLU, Hadamard Q4_0

[bong-water-water-bong]

llama.cpp fork commits since 6e42b51 (figures from each PR, Qwen3.8-27B on HRX0, balanced mode):

• PR-Agent: local coding model on the strixhalo runner #61: q8_1 x4 prefill takes the 256-aligned head of a Q5_K/IQ4_XS remainder chunk.
  UD-Q4_K_XL pp400 67.4 -> 103.4, pp1862 172.1 -> 234.6 tok/s; KLD vs 6e42b51 0.00215,
  same top token 97.19%; MUL_MAT HRX0 287/287.
• Build as C++26 #59: V stays row-major past copy_transpose_f16's 32768-row range. pp512 @ d32768 failed
  before, 227.4 tok/s now; a 34,816-token wikitext chunk gives PPL 6.2150.
• 1bit OS: the boot fixes the VM test found (after #56) #60: K-quant SwiGLU decode stages separate gate/up codebooks. UD-IQ2_S tg128 3.12 -> 8.32;
  UD-Q4_K_XL unchanged; KLD 0.00013; test-backend-ops HRX0 996/996.
• Lean: ROCmI4 on Vulkan (our ROCmFPX fork); the bump rebases our commit #58: llama loads onebit.hadamard_q4_0 files through llama-hadamard (needed by serve: Hadamard-rotated Q4_0 files run on --device hrx too #277).
  Q4_0-H32 vs BF16: PPL 6.021, KLD 0.0292, same top token 92.5%.

Docs: docs/hrx.md #55 section (remainders now covered for Q5_K/IQ4_XS) and "Our patches".
Registry regenerated (tools/registry_build.py; no mapping changes).

A smoke test of the combined pin (build, test-backend-ops MUL_MAT x2, llama-bench pp400/pp512/tg64 on Qwen3.8-27B UD-Q4_K_XL) is running on strixhalo; I'll post the results here.

Unblocks #276 (needs #59) and #277 (needs #58).

🤖 Generated with Claude Code

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Commit 446bff3

[bong-water-water-bong]

Review (PR-Agent duty): looks right. The submodule and registry/architectures.json both point at bd5b297; the registry diff is the one pin line. The #58, #59, #60 and #61 entries match the fork PRs and the figures their authors measured.

One labelling nit in the new #55/#61 table in docs/hrx.md: the right column says bd5b297, but those numbers (pp400 103.4, pp1862 234.6, KLD 0.00215) were measured on 6e42b51 + #61, which is a36d547 without #58-#60. #58-#60 don't touch the Q5_K/IQ4_XS prefill path, so I expect the same numbers on bd5b297. Either relabel the column 6e42b51 + #61, or keep bd5b297 once your combined-build smoke test (pp400) confirms it.

Fine to merge after the smoke test and build pass.

[bong-water-water-bong]

Smoke test of the combined pin on strixhalo (fork bd5b297, HRX0, balanced mode, box shared with other jobs):

• test-backend-ops -o MUL_MAT -b HRX0: 287/287, twice.
• Qwen3.8-27B UD-Q4_K_XL, llama-bench -b 512 -ub 512 -r 3: pp400 103.84 ± 0.43 (matches PR-Agent: local coding model on the strixhalo runner #61's 103.4), pp512 272 ± 60, tg64 10.2 ± 2.7.

The pp512 and tg64 spreads come from thermal-run pauses and other GPU jobs on the box, not from the pin. The numbers in the docs come from each fork PR's own measurements.

The #61 table column is relabelled to "6e42b51 + #61 (a36d547)" (review).