serve --parallel on HRX: shared KV cache, no qwen.attention (Qwen3-4B 4 slots 39 -> 153 tok/s)

app/serve.cpp

@@ -737,6 +737,22 @@ Launch launch_for(const Options& o, const std::string& device, int child_port) {
         // for all of them; llama-server splits --ctx-size across the slots
         if (device == "zinc" || device == "mlx" || device == "ds4") throw std::runtime_error("--parallel works on the llama.cpp devices (vulkan, hrx, rocm)");
         argv.insert(argv.end(), {"-np", std::to_string(o.parallel)});
+        if (device == "hrx") {
+            // HRX runs attention on the GPU only with one KV stream: -kvu shares one cache across
+            // the slots (per-slot streams are 4-D and its flash attention falls back to the CPU:
+            // Qwen3-4B, 4 slots, 39 -> 153 tok/s). AMD's Qwen attention path (qwen.attention) builds
+            // its mask from positions and ignores the other sequences, so under -kvu the answers
+            // bleed into each other; it is turned off for these servers.
+            const std::string arch = gguf_architecture(o.model);
+            if (arch == "qwen35" || arch == "qwen35moe" || arch == "qwen3next")
+                throw std::runtime_error("--parallel on --device hrx does not run " + arch +
+                                         " yet (no multi-sequence gated delta-net on HRX); use --device vulkan");
+            argv.push_back("-kvu");
+            bool merged = false;
+            for (std::string& e : env)
+                if (e.rfind("GGML_HRX_DISABLE_DISPATCH=", 0) == 0) { e += ",qwen.attention"; merged = true; }
+            if (!merged) env.push_back("GGML_HRX_DISABLE_DISPATCH=qwen.attention");
+        }
     }
     if (!o.mtp.empty() && !o.dflash.empty()) throw std::runtime_error("--mtp and --dflash are two drafters; pick one");
     if (!o.mtp.empty() || !o.dflash.empty()) {

docs/hrx.md

@@ -452,6 +452,15 @@ evictions: Qwen3-Coder-30B (2113-token prompt, partial alignment 256) went from
   22.5 / 17.7 / 19.0 tok/s on code / prose / translation prompts (was 20.1 / 16.4 / 17.6; Vulkan
   34.6 / 24.3 / 24.5) with the same draft acceptance. A 4-token step still costs ~1.7x a 1-token
   step (f32 multiply-adds per token); int8 activations, as Vulkan does, are the next step.
+- **`1bit serve --device hrx --parallel N`.** With one KV stream per slot, the K/V tensors are
+  4-D and HRX's flash attention falls back to the CPU in every layer (Qwen3-4B, 4 slots: 39 tok/s
+  aggregate, below one stream). serve now passes `-kvu` (one shared KV cache) and turns off AMD's
+  Qwen attention path (`qwen.attention`), which derives its mask from positions and let the slots'
+  answers bleed into each other under `-kvu`. Qwen3-4B 4 slots: 153 tok/s aggregate (single stream
+  76; Vulkan 216); Qwen3-Coder-30B-A3B 34 -> 74; ZAYA1-8B 47 -> 71. Hybrid gated delta-net models
+  (qwen35, qwen35moe, qwen3next: Qwen3.5/3.8) are refused with `--parallel` on HRX: there is no
+  multi-sequence GATED_DELTA_NET kernel yet ([llama.cpp #48](https://github.com/1bit-MONSTER/llama.cpp/pull/48)
+  fixed the two failures before it).
 - **Fast sub-4-bit kernels on HRX.** IQ2 matmuls still fall back to the CPU; IQ3_S has a decode
   kernel (#43) but not a fast prefill one.
 - **Q4NX on HRX.** Our Q4NX kernels lived in ggml-hrx2 and are not in ggml-hrx.

registry/architectures.json

@@ -2,7 +2,7 @@
  "about": "HF architecture -> GGUF architecture and the backends whose code accepts it. Generated by tools/registry_build.py from the pinned sources; do not edit.",
  "sources": {
   "llama.cpp (vulkan)": "cecf3ee01d9d99378e98bfea95f51cac714b04b8",
-  "llama.cpp (hrx)": "dad19addd99d23383a01a96c0363411d445769ba",
+  "llama.cpp (hrx)": "acf9c747c3a0046981604615db5d3306ea8f4c98",
   "zinc": "29bc350ac4cbf9f110ec628b9e177ea04ac816fb"
  },
  "counts": {