docs(vcr): traceability for parallel perf tracks B (clamp lowering) + C (R10 pool) (#242)#282
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…l, C) — traceability leads (#242) Per the measured ROI reframing (#209): the allocator (VCR-RA-001) is the north-star but register-pool-constrained, so its win is modest. gale's #209 decomposition puts the biggest single chunk in clamp lowering (18 IT-blocks vs native 6 — VCR-SEL-002, track B), and freeing R10 when bounds-checking is off is a cheap +1-register pressure multiplier (VCR-RA-002, track C). B + C run in parallel with A, disjoint code, gated by RESULT-identity (flight_seam 0x07FDF307) + measured delta, not byte-identity. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Traceability leads — parallel ROI tracks for the codegen perf work
Per the measured reframing on #209: the allocator (VCR-RA-001, track A) is the north-star but register-pool-constrained, so its measured win is modest. This files the two complementary, parallelizable levers gale's #209 decomposition surfaced:
[-127,127]lower to 18 IT-blocks vs native's 6 — gale's biggest single chunk. ARMSSATdoesn't apply ([-127,127] ≠ [-128,127]); the lever is a tighterSelect/conditional-move lowering. Disjoint from A.BoundsCheckConfig::{Software,Mpu,Masking}(verified). InNonemode it's a wasted reserve — a cheap +1 register (pool 9→10). Composes with A (which reads the pool from config).Parallelism: B, C, A touch disjoint code. B/C are optimizations (bytes change), so the gate is result-identity (
flight_seam 0x07FDF307) + measured delta, not byte-identity — which removes the only would-be conflict (no shared fixture re-freeze). Bothproposed; verification artifacts land with the oracle-gated code.rivet-clean (only the expected
proposed-requirement WARN, no ERROR).🤖 Generated with Claude Code