From 29868c9fbcc10d2afddf5ab8fdfc10d2e8745b63 Mon Sep 17 00:00:00 2001 From: shrutikbalwan Date: Sun, 27 Sep 2026 14:35:26 +0530 Subject: [PATCH] Document common Ibex development commands Signed-off-by: shrutikbalwan --- doc/02_user/getting_started.rst | 43 +++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/doc/02_user/getting_started.rst b/doc/02_user/getting_started.rst index e56b83004d..6b6150e416 100644 --- a/doc/02_user/getting_started.rst +++ b/doc/02_user/getting_started.rst @@ -16,3 +16,46 @@ There are several paths to follow depending on what you wish to accomplish: * See :ref:`verification` to begin working with the DV flow. * See :ref:`core-integration` to integrate the Ibex core into your own design. * See :ref:`integration-fusesoc-files` for information on how to get a complete RTL file listing to build Ibex for use outside of FuseSoC based flows. + +Common development tasks +------------------------ + +The top-level Makefile provides shortcuts for common build, simulation, and lint tasks. +Run these commands from the root of the Ibex repository after installing the tools listed in :doc:`system_requirements`. + +To build and run the Verilator-based Simple System example with the default ``small`` Ibex configuration: + +.. code-block:: bash + + make build-simple-system + make run-simple-system + +To build and run the control and status register (CSR) testbench with Verilator: + +.. code-block:: bash + + make build-csr-test + make run-csr-test + +The following commands run commonly used checks: + +.. code-block:: bash + + # Lint the core and instruction tracer RTL. + make lint-core-tracing + + # Lint the Python utilities. + make python-lint + + # Build the RISC-V compliance simulation target. + make build-riscv-compliance + +The RTL tasks use the ``small`` configuration by default. +Set ``IBEX_CONFIG`` to select another configuration from :file:`ibex_configs.yaml`, for example: + +.. code-block:: bash + + make IBEX_CONFIG=maxperf build-simple-system + +Use ``make test-cfg IBEX_CONFIG=`` to display the FuseSoC options for a configuration. +The full UVM verification environment requires additional tools and is described in :ref:`verification`.