diff --git a/llvm/test/Transforms/SLPVectorizer/X86/complex-fma-combine.ll b/llvm/test/Transforms/SLPVectorizer/X86/complex-fma-combine.ll
new file mode 100644
index 0000000000000..5c40ea7d79e89
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/complex-fma-combine.ll
@@ -0,0 +1,55 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux -mcpu=skylake < %s | FileCheck %s
+
+define <2 x float> @fma_f32(ptr %A, float %B) {
+; CHECK-LABEL: define <2 x float> @fma_f32(
+; CHECK-SAME: ptr [[A:%.*]], float [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    [[TMP0:%.*]] = load <2 x float>, ptr [[A]], align 4
+; CHECK-NEXT:    [[RETVAL_SROA_0_0_VEC_EXTRACT_I:%.*]] = extractelement <2 x float> [[TMP0]], i64 0
+; CHECK-NEXT:    [[RETVAL_SROA_0_4_VEC_EXTRACT_I:%.*]] = extractelement <2 x float> [[TMP0]], i64 1
+; CHECK-NEXT:    [[MUL_RL_I_I:%.*]] = fmul float [[RETVAL_SROA_0_0_VEC_EXTRACT_I]], 2.000000e+00
+; CHECK-NEXT:    [[MUL_IL_I_I:%.*]] = fmul float [[RETVAL_SROA_0_4_VEC_EXTRACT_I]], 2.000000e+00
+; CHECK-NEXT:    [[ADD_R_I_I:%.*]] = fadd float [[B]], [[MUL_RL_I_I]]
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> poison, float [[ADD_R_I_I]], i64 0
+; CHECK-NEXT:    [[RETVAL_SROA_0_0_VEC_INSERT_I6:%.*]] = insertelement <2 x float> [[TMP1]], float [[MUL_IL_I_I]], i64 1
+; CHECK-NEXT:    ret <2 x float> [[RETVAL_SROA_0_0_VEC_INSERT_I6]]
+;
+entry:
+  %0 = load <2 x float>, ptr %A, align 4
+  %retval.sroa.0.0.vec.extract.i = extractelement <2 x float> %0, i64 0
+  %retval.sroa.0.4.vec.extract.i = extractelement <2 x float> %0, i64 1
+  %mul.rl.i.i = fmul float %retval.sroa.0.0.vec.extract.i, 2.000000e+00
+  %mul.il.i.i = fmul float %retval.sroa.0.4.vec.extract.i, 2.000000e+00
+  %add.r.i.i = fadd float %B, %mul.rl.i.i
+  %1 = insertelement <2 x float> poison, float %add.r.i.i, i64 0
+  %retval.sroa.0.0.vec.insert.i6 = insertelement <2 x float> %1, float %mul.il.i.i, i64 1
+  ret <2 x float> %retval.sroa.0.0.vec.insert.i6
+}
+
+define { double, double } @fma_f64(ptr %A, double %B) {
+; CHECK-LABEL: define { double, double } @fma_f64(
+; CHECK-SAME: ptr [[A:%.*]], double [[B:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    [[RETVAL_SROA_0_0_COPYLOAD_I:%.*]] = load double, ptr [[A]], align 8
+; CHECK-NEXT:    [[RETVAL_SROA_4_0___Y_SROA_IDX_I:%.*]] = getelementptr inbounds nuw i8, ptr [[A]], i64 8
+; CHECK-NEXT:    [[RETVAL_SROA_4_0_COPYLOAD_I:%.*]] = load double, ptr [[RETVAL_SROA_4_0___Y_SROA_IDX_I]], align 8
+; CHECK-NEXT:    [[MUL_RL_I_I:%.*]] = fmul double [[RETVAL_SROA_0_0_COPYLOAD_I]], 2.000000e+00
+; CHECK-NEXT:    [[MUL_IL_I_I:%.*]] = fmul double [[RETVAL_SROA_4_0_COPYLOAD_I]], 2.000000e+00
+; CHECK-NEXT:    [[ADD_R_I_I:%.*]] = fadd double [[B]], [[MUL_RL_I_I]]
+; CHECK-NEXT:    [[DOTFCA_0_INSERT_I7:%.*]] = insertvalue { double, double } poison, double [[ADD_R_I_I]], 0
+; CHECK-NEXT:    [[DOTFCA_1_INSERT_I8:%.*]] = insertvalue { double, double } [[DOTFCA_0_INSERT_I7]], double [[MUL_IL_I_I]], 1
+; CHECK-NEXT:    ret { double, double } [[DOTFCA_1_INSERT_I8]]
+;
+entry:
+  %retval.sroa.0.0.copyload.i = load double, ptr %A, align 8
+  %retval.sroa.4.0.__y.sroa_idx.i = getelementptr inbounds nuw i8, ptr %A, i64 8
+  %retval.sroa.4.0.copyload.i = load double, ptr %retval.sroa.4.0.__y.sroa_idx.i, align 8
+  %mul.rl.i.i = fmul double %retval.sroa.0.0.copyload.i, 2.000000e+00
+  %mul.il.i.i = fmul double %retval.sroa.4.0.copyload.i, 2.000000e+00
+  %add.r.i.i = fadd double %B, %mul.rl.i.i
+  %.fca.0.insert.i7 = insertvalue { double, double } poison, double %add.r.i.i, 0
+  %.fca.1.insert.i8 = insertvalue { double, double } %.fca.0.insert.i7, double %mul.il.i.i, 1
+  ret { double, double } %.fca.1.insert.i8
+}
+