Skip to content

Commit f82892d

Browse files
bijudasgeertu
authored andcommitted
arm64: dts: renesas: r9a07g043: Add max-frequency to SDHI nodes
Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both SDHI0 and SDHI1 MMC controller nodes in the RZ/{G2UL,Five} (r9a07g043) device tree, increasing performance by ca. 33%. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260520115144.60067-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
1 parent daae3ec commit f82892d

1 file changed

Lines changed: 2 additions & 0 deletions

File tree

arch/arm64/boot/dts/renesas/r9a07g043.dtsi

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -655,6 +655,7 @@
655655
<&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
656656
<&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
657657
clock-names = "core", "clkh", "cd", "aclk";
658+
max-frequency = <133333333>;
658659
resets = <&cpg R9A07G043_SDHI0_IXRST>;
659660
power-domains = <&cpg>;
660661
status = "disabled";
@@ -671,6 +672,7 @@
671672
<&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
672673
<&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
673674
clock-names = "core", "clkh", "cd", "aclk";
675+
max-frequency = <133333333>;
674676
resets = <&cpg R9A07G043_SDHI1_IXRST>;
675677
power-domains = <&cpg>;
676678
status = "disabled";

0 commit comments

Comments
 (0)