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webgeek1234broonie
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spi: tegra210-quad: Allocate DMA memory for DMA engine
When the SPI controllers are running in DMA mode, it is the DMA engine that performs the memory accesses rather than the SPI controller. Pass the DMA engine's struct device pointer to the DMA API to make sure the correct DMA operations are used. Suggested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://patch.msgid.link/20260525-tegra194-qspi-iommu-v2-1-a11c53f804b2@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
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1 file changed

Lines changed: 18 additions & 11 deletions

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drivers/spi/spi-tegra210-quad.c

Lines changed: 18 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -226,11 +226,13 @@ struct tegra_qspi {
226226
struct completion xfer_completion;
227227
struct spi_transfer *curr_xfer;
228228

229+
struct device *rx_dma_dev;
229230
struct dma_chan *rx_dma_chan;
230231
u32 *rx_dma_buf;
231232
dma_addr_t rx_dma_phys;
232233
struct dma_async_tx_descriptor *rx_dma_desc;
233234

235+
struct device *tx_dma_dev;
234236
struct dma_chan *tx_dma_chan;
235237
u32 *tx_dma_buf;
236238
dma_addr_t tx_dma_phys;
@@ -574,15 +576,15 @@ static int tegra_qspi_dma_map_xfer(struct tegra_qspi *tqspi, struct spi_transfer
574576
len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4;
575577

576578
if (t->tx_buf) {
577-
t->tx_dma = dma_map_single(tqspi->dev, (void *)tx_buf, len, DMA_TO_DEVICE);
578-
if (dma_mapping_error(tqspi->dev, t->tx_dma))
579+
t->tx_dma = dma_map_single(tqspi->tx_dma_dev, (void *)tx_buf, len, DMA_TO_DEVICE);
580+
if (dma_mapping_error(tqspi->tx_dma_dev, t->tx_dma))
579581
return -ENOMEM;
580582
}
581583

582584
if (t->rx_buf) {
583-
t->rx_dma = dma_map_single(tqspi->dev, (void *)rx_buf, len, DMA_FROM_DEVICE);
584-
if (dma_mapping_error(tqspi->dev, t->rx_dma)) {
585-
dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE);
585+
t->rx_dma = dma_map_single(tqspi->rx_dma_dev, (void *)rx_buf, len, DMA_FROM_DEVICE);
586+
if (dma_mapping_error(tqspi->rx_dma_dev, t->rx_dma)) {
587+
dma_unmap_single(tqspi->tx_dma_dev, t->tx_dma, len, DMA_TO_DEVICE);
586588
return -ENOMEM;
587589
}
588590
}
@@ -597,9 +599,9 @@ static void tegra_qspi_dma_unmap_xfer(struct tegra_qspi *tqspi, struct spi_trans
597599
len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4;
598600

599601
if (t->tx_buf)
600-
dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE);
602+
dma_unmap_single(tqspi->tx_dma_dev, t->tx_dma, len, DMA_TO_DEVICE);
601603
if (t->rx_buf)
602-
dma_unmap_single(tqspi->dev, t->rx_dma, len, DMA_FROM_DEVICE);
604+
dma_unmap_single(tqspi->rx_dma_dev, t->rx_dma, len, DMA_FROM_DEVICE);
603605
}
604606

605607
static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct spi_transfer *t)
@@ -745,7 +747,7 @@ static int tegra_qspi_start_cpu_based_transfer(struct tegra_qspi *qspi, struct s
745747
static void tegra_qspi_deinit_dma(struct tegra_qspi *tqspi)
746748
{
747749
if (tqspi->tx_dma_buf) {
748-
dma_free_coherent(tqspi->dev, tqspi->dma_buf_size,
750+
dma_free_coherent(tqspi->tx_dma_dev, tqspi->dma_buf_size,
749751
tqspi->tx_dma_buf, tqspi->tx_dma_phys);
750752
tqspi->tx_dma_buf = NULL;
751753
}
@@ -756,7 +758,7 @@ static void tegra_qspi_deinit_dma(struct tegra_qspi *tqspi)
756758
}
757759

758760
if (tqspi->rx_dma_buf) {
759-
dma_free_coherent(tqspi->dev, tqspi->dma_buf_size,
761+
dma_free_coherent(tqspi->rx_dma_dev, tqspi->dma_buf_size,
760762
tqspi->rx_dma_buf, tqspi->rx_dma_phys);
761763
tqspi->rx_dma_buf = NULL;
762764
}
@@ -782,6 +784,7 @@ static int tegra_qspi_init_dma(struct tegra_qspi *tqspi)
782784
}
783785

784786
tqspi->rx_dma_chan = dma_chan;
787+
tqspi->rx_dma_dev = dmaengine_get_dma_device(tqspi->rx_dma_chan);
785788

786789
dma_chan = dma_request_chan(tqspi->dev, "tx");
787790
if (IS_ERR(dma_chan)) {
@@ -790,15 +793,19 @@ static int tegra_qspi_init_dma(struct tegra_qspi *tqspi)
790793
}
791794

792795
tqspi->tx_dma_chan = dma_chan;
796+
tqspi->tx_dma_dev = dmaengine_get_dma_device(tqspi->tx_dma_chan);
793797
} else {
794798
if (!device_iommu_mapped(tqspi->dev)) {
795799
dev_warn(tqspi->dev,
796800
"IOMMU not enabled in device-tree, falling back to PIO mode\n");
797801
return 0;
798802
}
803+
804+
tqspi->rx_dma_dev = tqspi->dev;
805+
tqspi->tx_dma_dev = tqspi->dev;
799806
}
800807

801-
dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL);
808+
dma_buf = dma_alloc_coherent(tqspi->rx_dma_dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL);
802809
if (!dma_buf) {
803810
err = -ENOMEM;
804811
goto err_out;
@@ -807,7 +814,7 @@ static int tegra_qspi_init_dma(struct tegra_qspi *tqspi)
807814
tqspi->rx_dma_buf = dma_buf;
808815
tqspi->rx_dma_phys = dma_phys;
809816

810-
dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL);
817+
dma_buf = dma_alloc_coherent(tqspi->tx_dma_dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL);
811818
if (!dma_buf) {
812819
err = -ENOMEM;
813820
goto err_out;

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