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morimoto
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arm64: dts: renesas: r8a78000: Add MFIS, MFIS-SCP, and transport nodes
Describe the MFIS and MFIS SCP instances which are used for various tasks including inter-processor communication. Remove the PRR node because it is part of MFIS on R-Car X5H and should be handled using the MFIS compatible. Also, describe the S-TCM transport area used for shared memory mailboxing. Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260519074702.3308-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Lines changed: 126 additions & 3 deletions

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‎arch/arm64/boot/dts/renesas/r8a78000.dtsi‎

Lines changed: 126 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -683,9 +683,123 @@
683683
#size-cells = <2>;
684684
ranges;
685685

686-
prr: chipid@189e0044 {
687-
compatible = "renesas,prr";
688-
reg = <0 0x189e0044 0 4>;
686+
mfis: system-controller@189e0000 {
687+
compatible = "renesas,r8a78000-mfis";
688+
reg = <0 0x189e0000 0 0x1000>, <0 0x18800000 0 0x40000>;
689+
reg-names = "common", "mboxes";
690+
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
723+
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
729+
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
730+
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
731+
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
732+
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
733+
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
734+
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
735+
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
736+
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
737+
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
738+
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
739+
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
740+
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
741+
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
742+
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
743+
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
744+
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
745+
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
746+
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
747+
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
748+
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
749+
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
750+
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
751+
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
752+
<GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
753+
<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
754+
interrupt-names = "ch0i", "ch0e", "ch1i", "ch1e", "ch2i", "ch2e", "ch3i", "ch3e",
755+
"ch4i", "ch4e", "ch5i", "ch5e", "ch6i", "ch6e", "ch7i", "ch7e",
756+
"ch8i", "ch8e", "ch9i", "ch9e", "ch10i", "ch10e", "ch11i", "ch11e",
757+
"ch12i", "ch12e", "ch13i", "ch13e", "ch14i", "ch14e", "ch15i", "ch15e",
758+
"ch16i", "ch16e", "ch17i", "ch17e", "ch18i", "ch18e", "ch19i", "ch19e",
759+
"ch20i", "ch20e", "ch21i", "ch21e", "ch22i", "ch22e", "ch23i", "ch23e",
760+
"ch24i", "ch24e", "ch25i", "ch25e", "ch26i", "ch26e", "ch27i", "ch27e",
761+
"ch28i", "ch28e", "ch29i", "ch29e", "ch30i", "ch30e", "ch31i", "ch31e",
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"ch32i", "ch32e", "ch33i", "ch33e", "ch34i", "ch34e", "ch35i", "ch35e",
763+
"ch36i", "ch36e", "ch37i", "ch37e", "ch38i", "ch38e", "ch39i", "ch39e",
764+
"ch40i", "ch40e", "ch41i", "ch41e", "ch42i", "ch42e", "ch43i", "ch43e",
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"ch44i", "ch44e", "ch45i", "ch45e", "ch46i", "ch46e", "ch47i", "ch47e",
766+
"ch48i", "ch48e", "ch49i", "ch49e", "ch50i", "ch50e", "ch51i", "ch51e",
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"ch52i", "ch52e", "ch53i", "ch53e", "ch54i", "ch54e", "ch55i", "ch55e",
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"ch56i", "ch56e", "ch57i", "ch57e", "ch58i", "ch58e", "ch59i", "ch59e",
769+
"ch60i", "ch60e", "ch61i", "ch61e", "ch62i", "ch62e", "ch63i", "ch63e";
770+
#mbox-cells = <2>;
771+
#hwlock-cells = <1>;
772+
status = "disabled";
773+
};
774+
775+
mfis_scp: system-controller@189e1000 {
776+
compatible = "renesas,r8a78000-mfis-scp";
777+
reg = <0 0x189e1000 0 0x1000>, <0 0x18840000 0 0x2c000>;
778+
reg-names = "common", "mboxes";
779+
interrupts = <GIC_ESPI 296 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 297 IRQ_TYPE_LEVEL_HIGH>,
780+
<GIC_ESPI 298 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 299 IRQ_TYPE_LEVEL_HIGH>,
781+
<GIC_ESPI 300 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 301 IRQ_TYPE_LEVEL_HIGH>,
782+
<GIC_ESPI 302 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 303 IRQ_TYPE_LEVEL_HIGH>,
783+
<GIC_ESPI 304 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 305 IRQ_TYPE_LEVEL_HIGH>,
784+
<GIC_ESPI 306 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 307 IRQ_TYPE_LEVEL_HIGH>,
785+
<GIC_ESPI 308 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 309 IRQ_TYPE_LEVEL_HIGH>,
786+
<GIC_ESPI 310 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 311 IRQ_TYPE_LEVEL_HIGH>,
787+
<GIC_ESPI 312 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 313 IRQ_TYPE_LEVEL_HIGH>,
788+
<GIC_ESPI 314 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 315 IRQ_TYPE_LEVEL_HIGH>,
789+
<GIC_ESPI 316 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 317 IRQ_TYPE_LEVEL_HIGH>,
790+
<GIC_ESPI 318 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 319 IRQ_TYPE_LEVEL_HIGH>,
791+
<GIC_ESPI 320 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 321 IRQ_TYPE_LEVEL_HIGH>,
792+
<GIC_ESPI 322 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 323 IRQ_TYPE_LEVEL_HIGH>,
793+
<GIC_ESPI 324 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 325 IRQ_TYPE_LEVEL_HIGH>,
794+
<GIC_ESPI 326 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 327 IRQ_TYPE_LEVEL_HIGH>;
795+
/* SCP uses I side IRQ only */
796+
interrupt-names = "ch0i", "ch1i", "ch2i", "ch3i", "ch4i", "ch5i", "ch6i", "ch7i",
797+
"ch8i", "ch9i", "ch10i", "ch11i", "ch12i", "ch13i", "ch14i", "ch15i",
798+
"ch16i", "ch17i", "ch18i", "ch19i", "ch20i", "ch21i", "ch22i", "ch23i",
799+
"ch24i", "ch25i", "ch26i", "ch27i", "ch28i", "ch29i", "ch30i", "ch31i";
800+
#mbox-cells = <2>;
801+
#hwlock-cells = <1>;
802+
status = "disabled";
689803
};
690804

691805
/* Application Processors manage View-1 of a GIC-720AE */
@@ -810,6 +924,15 @@
810924
clock-names = "fck", "brg_int", "scif_clk";
811925
status = "disabled";
812926
};
927+
928+
stcm_transport: sram@c1060000 {
929+
compatible = "mmio-sram";
930+
reg = <0x0 0xc1060000 0x0 0x1c00>;
931+
#address-cells = <1>;
932+
#size-cells = <1>;
933+
ranges = <0 0x0 0xc1060000 0x1c00>;
934+
/* actual transport nodes must be set per board file */
935+
};
813936
};
814937

815938
timer {

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