Skip to content

Commit 948b075

Browse files
John Madieubroonie
John Madieu
authored and
broonie
committed
ASoC: rsnd: Add RZ/G3E SoC probing and register map
RZ/G3E audio subsystem has a different register layout compared to R-Car Gen2/Gen3/Gen4, as described below: - Different base address organization (SCU, ADG, SSIU, SSI as separate regions accessed by name) - Additional registers: AUDIO_CLK_SEL3, SSI_MODE3, SSI_CONTROL2 - Different register offsets within each region Add RZ/G3E SoC's audio subsystem register layouts and probe support. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://patch.msgid.link/20260525110230.4014435-6-john.madieu.xa@bp.renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
1 parent 22622fa commit 948b075

3 files changed

Lines changed: 204 additions & 3 deletions

File tree

‎sound/soc/renesas/rcar/core.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -106,6 +106,7 @@ static const struct of_device_id rsnd_of_match[] = {
106106
{ .compatible = "renesas,rcar_sound-gen4", .data = (void *)RSND_GEN4 },
107107
/* Special Handling */
108108
{ .compatible = "renesas,rcar_sound-r8a77990", .data = (void *)(RSND_GEN3 | RSND_SOC_E) },
109+
{ .compatible = "renesas,r9a09g047-sound", .data = (void *)(RSND_RZ3 | RSND_RZG3E) },
109110
{},
110111
};
111112
MODULE_DEVICE_TABLE(of, rsnd_of_match);

‎sound/soc/renesas/rcar/gen.c‎

Lines changed: 180 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -464,6 +464,184 @@ static int rsnd_gen1_probe(struct rsnd_priv *priv)
464464
return ret_adg | ret_ssi;
465465
}
466466

467+
/*
468+
* RZ/G3E Generation
469+
*/
470+
static int rsnd_rzg3e_probe(struct rsnd_priv *priv)
471+
{
472+
static const struct rsnd_regmap_field_conf conf_ssiu[] = {
473+
RSND_GEN_S_REG(SSI_MODE1, 0x804),
474+
RSND_GEN_S_REG(SSI_MODE2, 0x808),
475+
RSND_GEN_S_REG(SSI_MODE3, 0x80c),
476+
RSND_GEN_S_REG(SSI_CONTROL, 0x810),
477+
RSND_GEN_S_REG(SSI_CONTROL2, 0x814),
478+
RSND_GEN_S_REG(SSI_SYS_STATUS0, 0x840),
479+
RSND_GEN_S_REG(SSI_SYS_STATUS1, 0x844),
480+
RSND_GEN_S_REG(SSI_SYS_STATUS2, 0x848),
481+
RSND_GEN_S_REG(SSI_SYS_STATUS3, 0x84c),
482+
RSND_GEN_S_REG(SSI_SYS_INT_ENABLE0, 0x850),
483+
RSND_GEN_S_REG(SSI_SYS_INT_ENABLE1, 0x854),
484+
RSND_GEN_S_REG(SSI_SYS_INT_ENABLE2, 0x858),
485+
RSND_GEN_S_REG(SSI_SYS_INT_ENABLE3, 0x85c),
486+
RSND_GEN_M_REG(SSI_BUSIF0_MODE, 0x0, 0x80),
487+
RSND_GEN_M_REG(SSI_BUSIF0_ADINR, 0x4, 0x80),
488+
RSND_GEN_M_REG(SSI_BUSIF0_DALIGN, 0x8, 0x80),
489+
RSND_GEN_M_REG(SSI_BUSIF1_MODE, 0x20, 0x80),
490+
RSND_GEN_M_REG(SSI_BUSIF1_ADINR, 0x24, 0x80),
491+
RSND_GEN_M_REG(SSI_BUSIF1_DALIGN, 0x28, 0x80),
492+
RSND_GEN_M_REG(SSI_BUSIF2_MODE, 0x40, 0x80),
493+
RSND_GEN_M_REG(SSI_BUSIF2_ADINR, 0x44, 0x80),
494+
RSND_GEN_M_REG(SSI_BUSIF2_DALIGN, 0x48, 0x80),
495+
RSND_GEN_M_REG(SSI_BUSIF3_MODE, 0x60, 0x80),
496+
RSND_GEN_M_REG(SSI_BUSIF3_ADINR, 0x64, 0x80),
497+
RSND_GEN_M_REG(SSI_BUSIF3_DALIGN, 0x68, 0x80),
498+
RSND_GEN_M_REG(SSI_MODE, 0xc, 0x80),
499+
RSND_GEN_M_REG(SSI_CTRL, 0x10, 0x80),
500+
RSND_GEN_M_REG(SSI_INT_ENABLE, 0x18, 0x80),
501+
RSND_GEN_S_REG(SSI9_BUSIF0_MODE, 0x480),
502+
RSND_GEN_S_REG(SSI9_BUSIF0_ADINR, 0x484),
503+
RSND_GEN_S_REG(SSI9_BUSIF0_DALIGN, 0x488),
504+
RSND_GEN_S_REG(SSI9_BUSIF1_MODE, 0x4a0),
505+
RSND_GEN_S_REG(SSI9_BUSIF1_ADINR, 0x4a4),
506+
RSND_GEN_S_REG(SSI9_BUSIF1_DALIGN, 0x4a8),
507+
RSND_GEN_S_REG(SSI9_BUSIF2_MODE, 0x4c0),
508+
RSND_GEN_S_REG(SSI9_BUSIF2_ADINR, 0x4c4),
509+
RSND_GEN_S_REG(SSI9_BUSIF2_DALIGN, 0x4c8),
510+
RSND_GEN_S_REG(SSI9_BUSIF3_MODE, 0x4e0),
511+
RSND_GEN_S_REG(SSI9_BUSIF3_ADINR, 0x4e4),
512+
RSND_GEN_S_REG(SSI9_BUSIF3_DALIGN, 0x4e8),
513+
};
514+
static const struct rsnd_regmap_field_conf conf_scu[] = {
515+
RSND_GEN_M_REG(SRC_I_BUSIF_MODE, 0x0, 0x20),
516+
RSND_GEN_M_REG(SRC_O_BUSIF_MODE, 0x4, 0x20),
517+
RSND_GEN_M_REG(SRC_BUSIF_DALIGN, 0x8, 0x20),
518+
RSND_GEN_M_REG(SRC_ROUTE_MODE0, 0xc, 0x20),
519+
RSND_GEN_M_REG(SRC_CTRL, 0x10, 0x20),
520+
RSND_GEN_M_REG(SRC_INT_ENABLE0, 0x18, 0x20),
521+
RSND_GEN_M_REG(CMD_BUSIF_MODE, 0x184, 0x20),
522+
RSND_GEN_M_REG(CMD_BUSIF_DALIGN, 0x188, 0x20),
523+
RSND_GEN_M_REG(CMD_ROUTE_SLCT, 0x18c, 0x20),
524+
RSND_GEN_M_REG(CMD_CTRL, 0x190, 0x20),
525+
RSND_GEN_S_REG(SCU_SYS_STATUS0, 0x1c8),
526+
RSND_GEN_S_REG(SCU_SYS_INT_EN0, 0x1cc),
527+
RSND_GEN_S_REG(SCU_SYS_STATUS1, 0x1d0),
528+
RSND_GEN_S_REG(SCU_SYS_INT_EN1, 0x1d4),
529+
RSND_GEN_M_REG(SRC_SWRSR, 0x200, 0x40),
530+
RSND_GEN_M_REG(SRC_SRCIR, 0x204, 0x40),
531+
RSND_GEN_M_REG(SRC_ADINR, 0x214, 0x40),
532+
RSND_GEN_M_REG(SRC_IFSCR, 0x21c, 0x40),
533+
RSND_GEN_M_REG(SRC_IFSVR, 0x220, 0x40),
534+
RSND_GEN_M_REG(SRC_SRCCR, 0x224, 0x40),
535+
RSND_GEN_M_REG(SRC_BSDSR, 0x22c, 0x40),
536+
RSND_GEN_M_REG(SRC_BSISR, 0x238, 0x40),
537+
RSND_GEN_M_REG(CTU_SWRSR, 0x500, 0x100),
538+
RSND_GEN_M_REG(CTU_CTUIR, 0x504, 0x100),
539+
RSND_GEN_M_REG(CTU_ADINR, 0x508, 0x100),
540+
RSND_GEN_M_REG(CTU_CPMDR, 0x510, 0x100),
541+
RSND_GEN_M_REG(CTU_SCMDR, 0x514, 0x100),
542+
RSND_GEN_M_REG(CTU_SV00R, 0x518, 0x100),
543+
RSND_GEN_M_REG(CTU_SV01R, 0x51c, 0x100),
544+
RSND_GEN_M_REG(CTU_SV02R, 0x520, 0x100),
545+
RSND_GEN_M_REG(CTU_SV03R, 0x524, 0x100),
546+
RSND_GEN_M_REG(CTU_SV04R, 0x528, 0x100),
547+
RSND_GEN_M_REG(CTU_SV05R, 0x52c, 0x100),
548+
RSND_GEN_M_REG(CTU_SV06R, 0x530, 0x100),
549+
RSND_GEN_M_REG(CTU_SV07R, 0x534, 0x100),
550+
RSND_GEN_M_REG(CTU_SV10R, 0x538, 0x100),
551+
RSND_GEN_M_REG(CTU_SV11R, 0x53c, 0x100),
552+
RSND_GEN_M_REG(CTU_SV12R, 0x540, 0x100),
553+
RSND_GEN_M_REG(CTU_SV13R, 0x544, 0x100),
554+
RSND_GEN_M_REG(CTU_SV14R, 0x548, 0x100),
555+
RSND_GEN_M_REG(CTU_SV15R, 0x54c, 0x100),
556+
RSND_GEN_M_REG(CTU_SV16R, 0x550, 0x100),
557+
RSND_GEN_M_REG(CTU_SV17R, 0x554, 0x100),
558+
RSND_GEN_M_REG(CTU_SV20R, 0x558, 0x100),
559+
RSND_GEN_M_REG(CTU_SV21R, 0x55c, 0x100),
560+
RSND_GEN_M_REG(CTU_SV22R, 0x560, 0x100),
561+
RSND_GEN_M_REG(CTU_SV23R, 0x564, 0x100),
562+
RSND_GEN_M_REG(CTU_SV24R, 0x568, 0x100),
563+
RSND_GEN_M_REG(CTU_SV25R, 0x56c, 0x100),
564+
RSND_GEN_M_REG(CTU_SV26R, 0x570, 0x100),
565+
RSND_GEN_M_REG(CTU_SV27R, 0x574, 0x100),
566+
RSND_GEN_M_REG(CTU_SV30R, 0x578, 0x100),
567+
RSND_GEN_M_REG(CTU_SV31R, 0x57c, 0x100),
568+
RSND_GEN_M_REG(CTU_SV32R, 0x580, 0x100),
569+
RSND_GEN_M_REG(CTU_SV33R, 0x584, 0x100),
570+
RSND_GEN_M_REG(CTU_SV34R, 0x588, 0x100),
571+
RSND_GEN_M_REG(CTU_SV35R, 0x58c, 0x100),
572+
RSND_GEN_M_REG(CTU_SV36R, 0x590, 0x100),
573+
RSND_GEN_M_REG(CTU_SV37R, 0x594, 0x100),
574+
RSND_GEN_M_REG(MIX_SWRSR, 0xd00, 0x40),
575+
RSND_GEN_M_REG(MIX_MIXIR, 0xd04, 0x40),
576+
RSND_GEN_M_REG(MIX_ADINR, 0xd08, 0x40),
577+
RSND_GEN_M_REG(MIX_MIXMR, 0xd10, 0x40),
578+
RSND_GEN_M_REG(MIX_MVPDR, 0xd14, 0x40),
579+
RSND_GEN_M_REG(MIX_MDBAR, 0xd18, 0x40),
580+
RSND_GEN_M_REG(MIX_MDBBR, 0xd1c, 0x40),
581+
RSND_GEN_M_REG(MIX_MDBCR, 0xd20, 0x40),
582+
RSND_GEN_M_REG(MIX_MDBDR, 0xd24, 0x40),
583+
RSND_GEN_M_REG(MIX_MDBER, 0xd28, 0x40),
584+
RSND_GEN_M_REG(DVC_SWRSR, 0xe00, 0x100),
585+
RSND_GEN_M_REG(DVC_DVUIR, 0xe04, 0x100),
586+
RSND_GEN_M_REG(DVC_ADINR, 0xe08, 0x100),
587+
RSND_GEN_M_REG(DVC_DVUCR, 0xe10, 0x100),
588+
RSND_GEN_M_REG(DVC_ZCMCR, 0xe14, 0x100),
589+
RSND_GEN_M_REG(DVC_VRCTR, 0xe18, 0x100),
590+
RSND_GEN_M_REG(DVC_VRPDR, 0xe1c, 0x100),
591+
RSND_GEN_M_REG(DVC_VRDBR, 0xe20, 0x100),
592+
RSND_GEN_M_REG(DVC_VOL0R, 0xe28, 0x100),
593+
RSND_GEN_M_REG(DVC_VOL1R, 0xe2c, 0x100),
594+
RSND_GEN_M_REG(DVC_VOL2R, 0xe30, 0x100),
595+
RSND_GEN_M_REG(DVC_VOL3R, 0xe34, 0x100),
596+
RSND_GEN_M_REG(DVC_VOL4R, 0xe38, 0x100),
597+
RSND_GEN_M_REG(DVC_VOL5R, 0xe3c, 0x100),
598+
RSND_GEN_M_REG(DVC_VOL6R, 0xe40, 0x100),
599+
RSND_GEN_M_REG(DVC_VOL7R, 0xe44, 0x100),
600+
RSND_GEN_M_REG(DVC_DVUER, 0xe48, 0x100),
601+
};
602+
static const struct rsnd_regmap_field_conf conf_adg[] = {
603+
RSND_GEN_S_REG(BRRA, 0x00),
604+
RSND_GEN_S_REG(BRRB, 0x04),
605+
RSND_GEN_S_REG(BRGCKR, 0x08),
606+
RSND_GEN_S_REG(AUDIO_CLK_SEL0, 0x0c),
607+
RSND_GEN_S_REG(AUDIO_CLK_SEL1, 0x10),
608+
RSND_GEN_S_REG(AUDIO_CLK_SEL2, 0x14),
609+
RSND_GEN_S_REG(AUDIO_CLK_SEL3, 0x18),
610+
RSND_GEN_S_REG(DIV_EN, 0x30),
611+
RSND_GEN_S_REG(SRCIN_TIMSEL0, 0x34),
612+
RSND_GEN_S_REG(SRCIN_TIMSEL1, 0x38),
613+
RSND_GEN_S_REG(SRCIN_TIMSEL2, 0x3c),
614+
RSND_GEN_S_REG(SRCIN_TIMSEL3, 0x40),
615+
RSND_GEN_S_REG(SRCIN_TIMSEL4, 0x44),
616+
RSND_GEN_S_REG(SRCOUT_TIMSEL0, 0x48),
617+
RSND_GEN_S_REG(SRCOUT_TIMSEL1, 0x4c),
618+
RSND_GEN_S_REG(SRCOUT_TIMSEL2, 0x50),
619+
RSND_GEN_S_REG(SRCOUT_TIMSEL3, 0x54),
620+
RSND_GEN_S_REG(SRCOUT_TIMSEL4, 0x58),
621+
RSND_GEN_S_REG(CMDOUT_TIMSEL, 0x5c),
622+
};
623+
static const struct rsnd_regmap_field_conf conf_ssi[] = {
624+
RSND_GEN_M_REG(SSICR, 0x00, 0x40),
625+
RSND_GEN_M_REG(SSISR, 0x04, 0x40),
626+
RSND_GEN_M_REG(SSIWSR, 0x20, 0x40),
627+
};
628+
int ret;
629+
630+
ret = rsnd_gen_regmap_init(priv, 10, RSND_BASE_SCU, "scu", conf_scu);
631+
if (ret < 0)
632+
return ret;
633+
634+
ret = rsnd_gen_regmap_init(priv, 1, RSND_BASE_ADG, "adg", conf_adg);
635+
if (ret < 0)
636+
return ret;
637+
638+
ret = rsnd_gen_regmap_init(priv, 10, RSND_BASE_SSIU, "ssiu", conf_ssiu);
639+
if (ret < 0)
640+
return ret;
641+
642+
return rsnd_gen_regmap_init(priv, 10, RSND_BASE_SSI, "ssi", conf_ssi);
643+
}
644+
467645
/*
468646
* Gen
469647
*/
@@ -487,6 +665,8 @@ int rsnd_gen_probe(struct rsnd_priv *priv)
487665
ret = rsnd_gen2_probe(priv);
488666
else if (rsnd_is_gen4(priv))
489667
ret = rsnd_gen4_probe(priv);
668+
else if (rsnd_is_rzg3e(priv))
669+
ret = rsnd_rzg3e_probe(priv);
490670

491671
if (ret < 0)
492672
dev_err(dev, "unknown generation R-Car sound device\n");

‎sound/soc/renesas/rcar/rsnd.h‎

Lines changed: 23 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -143,13 +143,16 @@ enum rsnd_reg {
143143
AUDIO_CLK_SEL0,
144144
AUDIO_CLK_SEL1,
145145
AUDIO_CLK_SEL2,
146+
AUDIO_CLK_SEL3,
146147

147148
/* SSIU */
148149
SSI_MODE,
149150
SSI_MODE0,
150151
SSI_MODE1,
151152
SSI_MODE2,
153+
SSI_MODE3,
152154
SSI_CONTROL,
155+
SSI_CONTROL2,
153156
SSI_CTRL,
154157
SSI_BUSIF0_MODE,
155158
SSI_BUSIF1_MODE,
@@ -641,14 +644,28 @@ struct rsnd_priv {
641644
struct platform_device *pdev;
642645
spinlock_t lock;
643646
unsigned long flags;
647+
648+
/*
649+
* Flags layout: 0xDCBA
650+
*
651+
* A: R-Car generation (Gen1/Gen2/Gen3/Gen4)
652+
* B: R-Car SoC variant (e.g. SOC_E for E1/E2/E3)
653+
* C: RZ series generation
654+
* D: RZ series SoC identifier (e.g. RZG3E)
655+
*
656+
* Bits 16+ are used for capability flags.
657+
*/
644658
#define RSND_GEN_MASK (0xF << 0)
645659
#define RSND_GEN1 (1 << 0)
646660
#define RSND_GEN2 (2 << 0)
647661
#define RSND_GEN3 (3 << 0)
648662
#define RSND_GEN4 (4 << 0)
649-
#define RSND_SOC_MASK (0xF << 4)
650-
#define RSND_SOC_E (1 << 4) /* E1/E2/E3 */
651-
663+
#define RSND_SOC_MASK (0xF << 4) /* nibble B */
664+
#define RSND_SOC_E (1 << 4) /* E1/E2/E3 */
665+
#define RSND_RZ_MASK (0xF << 8) /* nibble C */
666+
#define RSND_RZ3 (3 << 8)
667+
#define RSND_RZ_ID_MASK (0xF << 12) /* nibble D */
668+
#define RSND_RZG3E (1 << 12)
652669
/*
653670
* below value will be filled on rsnd_gen_probe()
654671
*/
@@ -727,6 +744,9 @@ struct rsnd_priv {
727744
#define rsnd_is_gen3_e3(priv) (((priv)->flags & \
728745
(RSND_GEN_MASK | RSND_SOC_MASK)) == \
729746
(RSND_GEN3 | RSND_SOC_E))
747+
#define rsnd_is_rzg3e(priv) (((priv)->flags & \
748+
(RSND_RZ_MASK | RSND_RZ_ID_MASK)) == \
749+
(RSND_RZ3 | RSND_RZG3E))
730750

731751
#define rsnd_flags_has(p, f) ((p)->flags & (f))
732752
#define rsnd_flags_set(p, f) ((p)->flags |= (f))

0 commit comments

Comments
 (0)