Skip to content

Commit 893227d

Browse files
Demon000geertu
Demon000
authored and
geertu
committed
arm64: dts: renesas: r9a09g087: Add MTU3 support
The Renesas RZ/N2H (R9A09G087) SoC has an MTU3 block. Add support for it. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260410163530.383818-11-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
1 parent f7abc1c commit 893227d

1 file changed

Lines changed: 68 additions & 0 deletions

File tree

‎arch/arm64/boot/dts/renesas/r9a09g087.dtsi‎

Lines changed: 68 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1119,6 +1119,74 @@
11191119
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
11201120
};
11211121

1122+
mtu3: timer@90001200 {
1123+
compatible = "renesas,r9a09g087-mtu3",
1124+
"renesas,rz-mtu3";
1125+
reg = <0 0x90001200 0 0xb00>;
1126+
interrupts = <GIC_SPI 420 IRQ_TYPE_EDGE_RISING>,
1127+
<GIC_SPI 421 IRQ_TYPE_EDGE_RISING>,
1128+
<GIC_SPI 422 IRQ_TYPE_EDGE_RISING>,
1129+
<GIC_SPI 423 IRQ_TYPE_EDGE_RISING>,
1130+
<GIC_SPI 424 IRQ_TYPE_EDGE_RISING>,
1131+
<GIC_SPI 425 IRQ_TYPE_EDGE_RISING>,
1132+
<GIC_SPI 426 IRQ_TYPE_EDGE_RISING>,
1133+
<GIC_SPI 427 IRQ_TYPE_EDGE_RISING>,
1134+
<GIC_SPI 428 IRQ_TYPE_EDGE_RISING>,
1135+
<GIC_SPI 429 IRQ_TYPE_EDGE_RISING>,
1136+
<GIC_SPI 430 IRQ_TYPE_EDGE_RISING>,
1137+
<GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
1138+
<GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
1139+
<GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
1140+
<GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
1141+
<GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
1142+
<GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
1143+
<GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
1144+
<GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
1145+
<GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
1146+
<GIC_SPI 440 IRQ_TYPE_EDGE_RISING>,
1147+
<GIC_SPI 441 IRQ_TYPE_EDGE_RISING>,
1148+
<GIC_SPI 442 IRQ_TYPE_EDGE_RISING>,
1149+
<GIC_SPI 443 IRQ_TYPE_EDGE_RISING>,
1150+
<GIC_SPI 444 IRQ_TYPE_EDGE_RISING>,
1151+
<GIC_SPI 445 IRQ_TYPE_EDGE_RISING>,
1152+
<GIC_SPI 446 IRQ_TYPE_EDGE_RISING>,
1153+
<GIC_SPI 447 IRQ_TYPE_EDGE_RISING>,
1154+
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1155+
<GIC_SPI 449 IRQ_TYPE_EDGE_RISING>,
1156+
<GIC_SPI 450 IRQ_TYPE_EDGE_RISING>,
1157+
<GIC_SPI 451 IRQ_TYPE_EDGE_RISING>,
1158+
<GIC_SPI 452 IRQ_TYPE_EDGE_RISING>,
1159+
<GIC_SPI 453 IRQ_TYPE_EDGE_RISING>,
1160+
<GIC_SPI 454 IRQ_TYPE_EDGE_RISING>,
1161+
<GIC_SPI 455 IRQ_TYPE_EDGE_RISING>,
1162+
<GIC_SPI 456 IRQ_TYPE_EDGE_RISING>,
1163+
<GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
1164+
<GIC_SPI 458 IRQ_TYPE_EDGE_RISING>,
1165+
<GIC_SPI 459 IRQ_TYPE_EDGE_RISING>,
1166+
<GIC_SPI 460 IRQ_TYPE_EDGE_RISING>,
1167+
<GIC_SPI 461 IRQ_TYPE_EDGE_RISING>,
1168+
<GIC_SPI 462 IRQ_TYPE_EDGE_RISING>;
1169+
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
1170+
"tciv0", "tgie0", "tgif0",
1171+
"tgia1", "tgib1", "tciv1", "tciu1",
1172+
"tgia2", "tgib2", "tciv2", "tciu2",
1173+
"tgia3", "tgib3", "tgic3", "tgid3",
1174+
"tciv3",
1175+
"tgia4", "tgib4", "tgic4", "tgid4",
1176+
"tciv4",
1177+
"tgiu5", "tgiv5", "tgiw5",
1178+
"tgia6", "tgib6", "tgic6", "tgid6",
1179+
"tciv6",
1180+
"tgia7", "tgib7", "tgic7", "tgid7",
1181+
"tciv7",
1182+
"tgia8", "tgib8", "tgic8", "tgid8",
1183+
"tciv8";
1184+
clocks = <&cpg CPG_MOD 200>;
1185+
power-domains = <&cpg>;
1186+
#pwm-cells = <3>;
1187+
status = "disabled";
1188+
};
1189+
11221190
adc0: adc@90014000 {
11231191
compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc";
11241192
reg = <0 0x90014000 0 0x400>;

0 commit comments

Comments
 (0)