Skip to content

Commit 556304b

Browse files
geertugeertu
committed
Merge tag 'renesas-r8a78000-dt-binding-defs-tag1' into renesas-dts-for-v7.2
Renesas R-Car X5H MFIS DT Binding Definitions DT bindings and binding definitions for the Renesas R-Car X5H (R8A78000) Multifunctional Interface (MFIS), shared by driver and DT source files.
2 parents a3904c5 + 0f63ba1 commit 556304b

2 files changed

Lines changed: 215 additions & 0 deletions

File tree

‎Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml‎

Lines changed: 187 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,187 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/soc/renesas/renesas,r8a78000-mfis.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Renesas MFIS (Multifunctional Interface) controller
8+
9+
maintainers:
10+
- Wolfram Sang <wsa+renesas@sang-engineering.com>
11+
12+
description:
13+
The Renesas Multifunctional Interface (MFIS) provides various functionality
14+
like mailboxes, hardware spinlocks, product identification, error injection,
15+
error detection and such. Parts of it can be used for communication between
16+
different CPU cores. Those cores can be in various domains like AP, RT, or
17+
SCP. Often multiple domain-specific MFIS instances exist in one SoC.
18+
19+
properties:
20+
compatible:
21+
enum:
22+
- renesas,r8a78000-mfis # R-Car X5H (AP<->AP, with PRR)
23+
- renesas,r8a78000-mfis-scp # R-Car X5H (AP<->SCP, without PRR)
24+
25+
reg:
26+
maxItems: 2
27+
28+
reg-names:
29+
items:
30+
- const: common
31+
- const: mboxes
32+
33+
interrupts:
34+
minItems: 32
35+
maxItems: 128
36+
description:
37+
The interrupts raised by the remote doorbells.
38+
39+
interrupt-names:
40+
minItems: 32
41+
maxItems: 128
42+
description:
43+
An interrupt name is constructed with the prefix 'ch'. Then, the
44+
channel number as specified in the documentation of the SoC. Finally,
45+
the letter 'i' if the interrupt is raised by the IICR register. Or 'e'
46+
if it is raised by the EICR register.
47+
48+
"#hwlock-cells":
49+
const: 1
50+
51+
"#mbox-cells":
52+
const: 2
53+
description:
54+
The first cell is the channel number as specified in the documentation
55+
of the SoC. The second cell may specify flags as described in the file
56+
<dt-bindings/soc/renesas,r8a78000-mfis.h>.
57+
58+
allOf:
59+
- if:
60+
properties:
61+
compatible:
62+
contains:
63+
const: renesas,r8a78000-mfis
64+
then:
65+
properties:
66+
interrupts:
67+
minItems: 128
68+
interrupt-names:
69+
minItems: 128
70+
items:
71+
pattern: "^ch[0-9]+[ie]$"
72+
73+
- if:
74+
properties:
75+
compatible:
76+
contains:
77+
const: renesas,r8a78000-mfis-scp
78+
then:
79+
properties:
80+
interrupts:
81+
maxItems: 32
82+
interrupt-names:
83+
maxItems: 32
84+
items:
85+
pattern: "^ch[0-9]+i$"
86+
87+
required:
88+
- compatible
89+
- reg
90+
- reg-names
91+
- interrupts
92+
- interrupt-names
93+
- "#hwlock-cells"
94+
- "#mbox-cells"
95+
96+
additionalProperties: false
97+
98+
examples:
99+
- |
100+
#include <dt-bindings/interrupt-controller/arm-gic.h>
101+
system-controller@189e0000 {
102+
compatible = "renesas,r8a78000-mfis";
103+
reg = <0x189e0000 0x1000>, <0x18800000 0x40000>;
104+
reg-names = "common", "mboxes";
105+
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
106+
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
107+
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
108+
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
109+
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
110+
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
111+
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
112+
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
113+
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
114+
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
115+
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
116+
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
117+
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
118+
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
119+
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
120+
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
121+
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
122+
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
123+
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
124+
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
125+
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
126+
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
127+
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
128+
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
129+
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
130+
<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
131+
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
132+
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
133+
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
134+
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
135+
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
136+
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
137+
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
138+
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
139+
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
140+
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
141+
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
142+
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
143+
<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
144+
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
145+
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
146+
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
147+
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
148+
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
149+
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
150+
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
151+
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
152+
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
153+
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
154+
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
155+
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
156+
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
157+
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
158+
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
159+
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
160+
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
161+
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
162+
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
163+
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
164+
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
165+
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
166+
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
167+
<GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
168+
<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
169+
interrupt-names = "ch0i", "ch0e", "ch1i", "ch1e", "ch2i", "ch2e", "ch3i", "ch3e",
170+
"ch4i", "ch4e", "ch5i", "ch5e", "ch6i", "ch6e", "ch7i", "ch7e",
171+
"ch8i", "ch8e", "ch9i", "ch9e", "ch10i", "ch10e", "ch11i", "ch11e",
172+
"ch12i", "ch12e", "ch13i", "ch13e", "ch14i", "ch14e", "ch15i", "ch15e",
173+
"ch16i", "ch16e", "ch17i", "ch17e", "ch18i", "ch18e", "ch19i", "ch19e",
174+
"ch20i", "ch20e", "ch21i", "ch21e", "ch22i", "ch22e", "ch23i", "ch23e",
175+
"ch24i", "ch24e", "ch25i", "ch25e", "ch26i", "ch26e", "ch27i", "ch27e",
176+
"ch28i", "ch28e", "ch29i", "ch29e", "ch30i", "ch30e", "ch31i", "ch31e",
177+
"ch32i", "ch32e", "ch33i", "ch33e", "ch34i", "ch34e", "ch35i", "ch35e",
178+
"ch36i", "ch36e", "ch37i", "ch37e", "ch38i", "ch38e", "ch39i", "ch39e",
179+
"ch40i", "ch40e", "ch41i", "ch41e", "ch42i", "ch42e", "ch43i", "ch43e",
180+
"ch44i", "ch44e", "ch45i", "ch45e", "ch46i", "ch46e", "ch47i", "ch47e",
181+
"ch48i", "ch48e", "ch49i", "ch49e", "ch50i", "ch50e", "ch51i", "ch51e",
182+
"ch52i", "ch52e", "ch53i", "ch53e", "ch54i", "ch54e", "ch55i", "ch55e",
183+
"ch56i", "ch56e", "ch57i", "ch57e", "ch58i", "ch58e", "ch59i", "ch59e",
184+
"ch60i", "ch60e", "ch61i", "ch61e", "ch62i", "ch62e", "ch63i", "ch63e";
185+
#hwlock-cells = <1>;
186+
#mbox-cells = <2>;
187+
};

‎include/dt-bindings/soc/renesas,r8a78000-mfis.h‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2+
#ifndef _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H
3+
#define _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H
4+
5+
/*
6+
* Constants for the second mbox-cell of the Renesas MFIS IP core. To be treated
7+
* as bit flags which can be ORed.
8+
*/
9+
10+
/*
11+
* MFIS HW design before r8a78001 requires a channel to be marked as either
12+
* TX or RX.
13+
*/
14+
#define MFIS_CHANNEL_TX (0 << 0)
15+
#define MFIS_CHANNEL_RX (1 << 0)
16+
17+
/*
18+
* MFIS variants before r8a78001 work with pairs of IICR and EICR registers.
19+
* Usually, it is specified in the datasheets which of the two a specific core
20+
* should use. Then, it does not need extra description in DT. For plain MFIS
21+
* of r8a78000, this is selectable, though. According to the system design and
22+
* the firmware in use, these channels need to be marked. This is not needed
23+
* with other versions of the MFIS, not even with MFIS-SCP of r8a78000.
24+
*/
25+
#define MFIS_CHANNEL_IICR (0 << 1)
26+
#define MFIS_CHANNEL_EICR (1 << 1)
27+
28+
#endif /* _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H */

0 commit comments

Comments
 (0)