Merge tag 'zx29-docfix-for-7.2' of https://gitlab.com/stefandoesinger/zx297520-kernel into soc/arm

ARM: zte: clean up zx297520v3 doc. warnings

This pull request contains fixes for building the zx29 SoC documentation
contributed by Randy Dunlap.

* tag 'zx29-docfix-for-7.2' of https://gitlab.com/stefandoesinger/zx297520-kernel:
  ARM: zte: clean up zx297520v3 doc. warnings

Signed-off-by: Linus Walleij <linusw@kernel.org>

Author: linusw

Documentation/arch/arm/zte/zx297520v3.rst

@@ -4,15 +4,13 @@
 Booting Linux on ZTE zx297520v3 SoCs
 ====================================
 
-...............................................................................
-
 Author:	Stefan Dösinger
 
 Date  : 27 Jan 2026
 
 1. Hardware description
 ---------------------------
-Zx297520v3 SoCs use a 64 bit capable Cortex-A53 CPU and GICv3, although they
+Zx297520v3 SoCs use a 64-bit capable Cortex-A53 CPU and GICv3, although they
 run in arm32 mode only. The CPU has support EL3, but no hypervisor (EL2) and
 it seems to lack VFP and NEON.
 
@@ -27,7 +25,7 @@ Some devices, especially the stationary ones, have 100 mbit Ethernet and an
 Ethernet switch.
 
 Usually the devices have LEDs for status indication, although some have SPI or
-I2C connected displays
+I2C connected displays.
 
 Some have an SD card slot. If it exists, it is a better choice for the root
 file system because it easily outperforms the built-in NAND.
@@ -39,7 +37,7 @@ IRQs on either ends.
 
 There is also a Cortex M0 CPU, which is responsible for early HW initialization
 and starting the Cortex A53 CPU. It does not have any essential purpose once
-U-Boot is started. A SRAM-Based handover protocol exists to run custom code on
+U-Boot is started. An SRAM-based handover protocol exists to run custom code on
 this CPU.
 
 2. Booting via USB
@@ -63,13 +61,13 @@ Contains an U-Boot version that can be used with the USB loader and sets up the
 CPU and interrupt controller to comply with Linux's booting requirements.
 
 3. Building for built-in U-Boot
----------------------------
+-------------------------------
 The devices come with an ancient U-Boot that loads legacy uImages from NAND and
 boots them without a chance for the user to interrupt. The images are stored in
 files ap_cpuap.bin and ap_recovery.bin on a jffs2 partition named imagefs,
 usually mtd4. A file named "fotaflag" switches between the two modes.
 
-In addition to the uImage header, those files have a 384 byte signature header,
+In addition to the uImage header, those files have a 384-byte signature header,
 which is used for authenticating the images on some devices. Most devices have
 this authentication disabled and it is enough to pad the uImage files with 384
 zero bytes.
@@ -88,7 +86,7 @@ So to build an image that boots from NAND the following steps are necessary:
 6) dd if=/dev/zero bs=1 count=384 of=ap_recovery.bin
 7) cat uimg >> ap_recovery.bin
 8) Place this file onto imagefs on the device. Delete ap_cpuap.bin if the
-free space is not enough.
+   free space is not enough.
 9) Create the file fotaflag: echo -n FOTA-RECOVERY > fotaflag
 
 For development, booting ap_recovery.bin is recommended because the normal boot
@@ -113,55 +111,56 @@ the binary blobs.
 
 The assembly code below is given as an example of how to achieve this:
 
-```
-#include <linux/irqchip/arm-gic-v3.h>
-#include <asm/assembler.h>
-#include <asm/cp15.h>
-
-@ Detect sane bootloaders and skip the hack
-ldr	r3, =0xf2000000
-ldr	r3, [r3]
-ldr	r4, =(GICD_CTLR_ARE_NS | GICD_CTLR_DS)
-cmp	r3, r4
-beq	skip_zx_hack
-@ This allows EL1 to handle ints hat are normally handled by EL2/3.
-ldr	r3, =0xf2000000
-str     r4, [r3]
-
-cps     #MON_MODE
-
-@ Work in non-secure physical address space: SCR_EL3.NS = 1. At least the UART
-@ seems to respond only to non-secure addresses. I have taken insipiration from
-@ Raspberry pi's armstub7.S here.
-mov	r3, #0x131			@ non-secure, Make F, A bits in CPSR writeable
-					@ Allow hypervisor call.
-mcr     p15, 0, r3, c1, c1, 0
-
-@ AP_PPI_MODE_REG: Configure timer PPIs (10, 11, 13, 14) to active-low.
-ldr	r3, =0xF22020a8
-ldr	r4, =0x50
-str	r4, [r3]
-ldr	r3, =0xF22020ac
-ldr	r4, =0x14
-str	r4, [r3]
-
-@ Enable EL2 access to ICC_SRE (bit 3, ICC_SRE_EL3.Enable). Enable system reg
-@ access to GICv3 registers (bit 0, ICC_SRE_EL3.SRE) for EL1 and EL3.
-mrc	p15, 6, r3, c12, c12, 5         @ ICC_SRE_EL3
-orr	r3, #0x9                        @ FIXME: No defines for SRE_EL3 values?
-mcr	p15, 6, r3, c12, c12, 5
-mrc	p15, 0, r3, c12, c12, 5         @ ICC_SRE_EL1
-orr	r3, #(ICC_SRE_EL1_SRE)
-mcr	p15, 0, r3, c12, c12, 5
-
-@ Like ICC_SRE_EL3, enable EL1 access to ICC_SRE and system register access
-@ for EL2.
-mrc	p15, 4, r3, c12, c9, 5          @ ICC_SRE_EL2 aka ICC_HSRE
-orr	r3, r3, #(ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_SRE)
-mcr	p15, 4, r3, c12, c9, 5
-isb
-
-@ Back to SVC mode
-cps	#SVC_MODE
-skip_zx_hack:
-```
+::
+
+ #include <linux/irqchip/arm-gic-v3.h>
+ #include <asm/assembler.h>
+ #include <asm/cp15.h>
+
+ @ Detect sane bootloaders and skip the hack
+ ldr	r3, =0xf2000000
+ ldr	r3, [r3]
+ ldr	r4, =(GICD_CTLR_ARE_NS | GICD_CTLR_DS)
+ cmp	r3, r4
+ beq	skip_zx_hack
+ @ This allows EL1 to handle ints hat are normally handled by EL2/3.
+ ldr	r3, =0xf2000000
+ str     r4, [r3]
+
+ cps     #MON_MODE
+
+ @ Work in non-secure physical address space: SCR_EL3.NS = 1. At least the UART
+ @ seems to respond only to non-secure addresses. I have taken insipiration from
+ @ Raspberry pi's armstub7.S here.
+ mov	r3, #0x131			@ non-secure, Make F, A bits in CPSR writeable
+ @ Allow hypervisor call.
+ mcr     p15, 0, r3, c1, c1, 0
+
+ @ AP_PPI_MODE_REG: Configure timer PPIs (10, 11, 13, 14) to active-low.
+ ldr	r3, =0xF22020a8
+ ldr	r4, =0x50
+ str	r4, [r3]
+ ldr	r3, =0xF22020ac
+ ldr	r4, =0x14
+ str	r4, [r3]
+
+ @ Enable EL2 access to ICC_SRE (bit 3, ICC_SRE_EL3.Enable). Enable system reg
+ @ access to GICv3 registers (bit 0, ICC_SRE_EL3.SRE) for EL1 and EL3.
+ mrc	p15, 6, r3, c12, c12, 5         @ ICC_SRE_EL3
+ orr	r3, #0x9                        @ FIXME: No defines for SRE_EL3 values?
+ mcr	p15, 6, r3, c12, c12, 5
+ mrc	p15, 0, r3, c12, c12, 5         @ ICC_SRE_EL1
+ orr	r3, #(ICC_SRE_EL1_SRE)
+ mcr	p15, 0, r3, c12, c12, 5
+
+ @ Like ICC_SRE_EL3, enable EL1 access to ICC_SRE and system register access
+ @ for EL2.
+ mrc	p15, 4, r3, c12, c9, 5          @ ICC_SRE_EL2 aka ICC_HSRE
+ orr	r3, r3, #(ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_SRE)
+ mcr	p15, 4, r3, c12, c9, 5
+ isb
+
+ @ Back to SVC mode
+ cps	#SVC_MODE
+ skip_zx_hack:
+