From a86682f1d7d3fc1bd90a8bb9ee4ee4b4e4c11aa6 Mon Sep 17 00:00:00 2001 From: Nanami Wang <36569033@qq.com> Date: Sat, 8 Dec 2018 15:13:09 -0600 Subject: [PATCH 01/10] Add FlexRay code --- cereal/log.capnp | 7 + common/params.py | 3 + flexray_adapter/.gitignore | 1 + flexray_adapter/README.md | 155 + flexray_adapter/__init__.py | 0 flexray_adapter/flexray_adapter/.cproject | 659 + .../flexray_adapter/.flexray_adapter.g_c | 1119 + .../flexray_adapter/.flexray_adapter.g_x | 376 + flexray_adapter/flexray_adapter/.gitignore | 3 + flexray_adapter/flexray_adapter/.project | 1617 + .../com.freescale.s32ds.cross.wizard.prefs | 17 + ...ssorexpert.core.ide.newprojectwizard.prefs | 2 + .../.settings/language.settings.xml | 36 + ...flexray_adapter_debug_flash_pemicro.launch | 174 + .../flexray_adapter_debug_ram_pemicro.launch | 174 + ...flexray_adapter_debug_ram_pemicro_2.launch | 174 + .../Documentation/flexray_adapter.txt | 350 + .../flexray_adapter_Settings.previous.xml | 117 + .../flexray_adapter_Settings.xml | 145 + .../flexray_adapter/Generated_Code/Cpu.c | 77 + .../flexray_adapter/Generated_Code/Cpu.h | 96 + .../Generated_Code/FreeRTOSConfig.h | 190 + .../Generated_Code/clockMan1.c | 818 + .../Generated_Code/clockMan1.h | 98 + .../Generated_Code/dmaController1.c | 91 + .../Generated_Code/dmaController1.h | 122 + .../Generated_Code/linflexd_uart1.c | 81 + .../Generated_Code/linflexd_uart1.h | 96 + .../flexray_adapter/Generated_Code/lwipcfg.h | 68 + .../flexray_adapter/Generated_Code/lwipopts.h | 291 + .../Generated_Code/lwippools.h | 56 + .../flexray_adapter/Generated_Code/pin_mux.c | 949 + .../flexray_adapter/Generated_Code/pin_mux.h | 3193 + .../flexray_adapter/ProcessorExpert.pe | 52672 ++++++++++++++++ .../Linker_Files/MPC5748G_flash.ld | 293 + .../Linker_Files/MPC5748G_ram.ld | 267 + .../flexray_adapter/Sources/event.h | 15 + .../flexray_adapter/Sources/flexray_config.c | 106 + .../flexray_adapter/Sources/flexray_config.h | 167 + .../flexray_adapter/Sources/flexray_driver.c | 1625 + .../flexray_adapter/Sources/flexray_driver.h | 89 + .../Sources/flexray_registers.h | 300 + .../Sources/flexray_state_machine.c | 289 + .../Sources/flexray_state_machine.h | 43 + .../flexray_adapter/Sources/main.c | 85 + .../flexray_adapter/Sources/packet.h | 42 + .../flexray_adapter/Sources/platform_defs.c | 8 + .../flexray_adapter/Sources/platform_defs.h | 36 + .../flexray_adapter/Sources/tcp_interface.c | 231 + .../flexray_adapter/Sources/tcp_interface.h | 24 + .../flexray_adapter/Sources/tcpip_stack.c | 132 + .../flexray_adapter/Sources/tcpip_stack.h | 15 + flexray_adapter/python/.gitignore | 2 + flexray_adapter/python/__init__.py | 0 flexray_adapter/python/constants.py | 108 + flexray_adapter/python/flexray_config.py | 430 + flexray_adapter/python/flexray_tool.py | 1235 + flexray_adapter/python/requirements.txt | 2 + flexray_adapter/python/tcp_interface.py | 139 + flexray_adapter/python/test/node1.yml | 239 + flexray_adapter/python/test/node2.yml | 207 + selfdrive/car/toyota/values.py | 4 + selfdrive/flexrayd/Makefile | 88 + selfdrive/flexrayd/flexrayd | Bin 0 -> 3875720 bytes selfdrive/flexrayd/flexrayd.cc | 379 + selfdrive/flexrayd/flexrayd_test.py | 93 + selfdrive/service_list.yaml | 3 +- 67 files changed, 70722 insertions(+), 1 deletion(-) create mode 100644 flexray_adapter/.gitignore create mode 100644 flexray_adapter/README.md create mode 100644 flexray_adapter/__init__.py create mode 100644 flexray_adapter/flexray_adapter/.cproject create mode 100644 flexray_adapter/flexray_adapter/.flexray_adapter.g_c create mode 100644 flexray_adapter/flexray_adapter/.flexray_adapter.g_x create mode 100644 flexray_adapter/flexray_adapter/.gitignore create mode 100644 flexray_adapter/flexray_adapter/.project create mode 100644 flexray_adapter/flexray_adapter/.settings/com.freescale.s32ds.cross.wizard.prefs create mode 100644 flexray_adapter/flexray_adapter/.settings/com.processorexpert.core.ide.newprojectwizard.prefs create mode 100644 flexray_adapter/flexray_adapter/.settings/language.settings.xml create mode 100644 flexray_adapter/flexray_adapter/Debug_Configurations/flexray_adapter_debug_flash_pemicro.launch create mode 100644 flexray_adapter/flexray_adapter/Debug_Configurations/flexray_adapter_debug_ram_pemicro.launch create mode 100644 flexray_adapter/flexray_adapter/Debug_Configurations/flexray_adapter_debug_ram_pemicro_2.launch create mode 100644 flexray_adapter/flexray_adapter/Documentation/flexray_adapter.txt create mode 100644 flexray_adapter/flexray_adapter/Documentation/flexray_adapter_Settings.previous.xml create mode 100644 flexray_adapter/flexray_adapter/Documentation/flexray_adapter_Settings.xml create mode 100644 flexray_adapter/flexray_adapter/Generated_Code/Cpu.c create mode 100644 flexray_adapter/flexray_adapter/Generated_Code/Cpu.h create mode 100644 flexray_adapter/flexray_adapter/Generated_Code/FreeRTOSConfig.h create mode 100644 flexray_adapter/flexray_adapter/Generated_Code/clockMan1.c create mode 100644 flexray_adapter/flexray_adapter/Generated_Code/clockMan1.h create mode 100644 flexray_adapter/flexray_adapter/Generated_Code/dmaController1.c create mode 100644 flexray_adapter/flexray_adapter/Generated_Code/dmaController1.h create mode 100644 flexray_adapter/flexray_adapter/Generated_Code/linflexd_uart1.c create mode 100644 flexray_adapter/flexray_adapter/Generated_Code/linflexd_uart1.h create mode 100644 flexray_adapter/flexray_adapter/Generated_Code/lwipcfg.h create mode 100644 flexray_adapter/flexray_adapter/Generated_Code/lwipopts.h create mode 100644 flexray_adapter/flexray_adapter/Generated_Code/lwippools.h create mode 100644 flexray_adapter/flexray_adapter/Generated_Code/pin_mux.c create mode 100644 flexray_adapter/flexray_adapter/Generated_Code/pin_mux.h create mode 100644 flexray_adapter/flexray_adapter/ProcessorExpert.pe create mode 100644 flexray_adapter/flexray_adapter/Project_Settings/Linker_Files/MPC5748G_flash.ld create mode 100644 flexray_adapter/flexray_adapter/Project_Settings/Linker_Files/MPC5748G_ram.ld create mode 100644 flexray_adapter/flexray_adapter/Sources/event.h create mode 100644 flexray_adapter/flexray_adapter/Sources/flexray_config.c create mode 100644 flexray_adapter/flexray_adapter/Sources/flexray_config.h create mode 100644 flexray_adapter/flexray_adapter/Sources/flexray_driver.c create mode 100644 flexray_adapter/flexray_adapter/Sources/flexray_driver.h create mode 100644 flexray_adapter/flexray_adapter/Sources/flexray_registers.h create mode 100644 flexray_adapter/flexray_adapter/Sources/flexray_state_machine.c create mode 100644 flexray_adapter/flexray_adapter/Sources/flexray_state_machine.h create mode 100644 flexray_adapter/flexray_adapter/Sources/main.c create mode 100644 flexray_adapter/flexray_adapter/Sources/packet.h create mode 100644 flexray_adapter/flexray_adapter/Sources/platform_defs.c create mode 100644 flexray_adapter/flexray_adapter/Sources/platform_defs.h create mode 100644 flexray_adapter/flexray_adapter/Sources/tcp_interface.c create mode 100644 flexray_adapter/flexray_adapter/Sources/tcp_interface.h create mode 100644 flexray_adapter/flexray_adapter/Sources/tcpip_stack.c create mode 100644 flexray_adapter/flexray_adapter/Sources/tcpip_stack.h create mode 100644 flexray_adapter/python/.gitignore create mode 100644 flexray_adapter/python/__init__.py create mode 100644 flexray_adapter/python/constants.py create mode 100644 flexray_adapter/python/flexray_config.py create mode 100644 flexray_adapter/python/flexray_tool.py create mode 100644 flexray_adapter/python/requirements.txt create mode 100644 flexray_adapter/python/tcp_interface.py create mode 100644 flexray_adapter/python/test/node1.yml create mode 100644 flexray_adapter/python/test/node2.yml create mode 100644 selfdrive/flexrayd/Makefile create mode 100755 selfdrive/flexrayd/flexrayd create mode 100644 selfdrive/flexrayd/flexrayd.cc create mode 100755 selfdrive/flexrayd/flexrayd_test.py diff --git a/cereal/log.capnp b/cereal/log.capnp index 389b550ad421ae..1dc36c155f0c5a 100644 --- a/cereal/log.capnp +++ b/cereal/log.capnp @@ -254,6 +254,11 @@ struct CanData { src @3 :UInt8; } +struct FlexRayData { + frameId @0 :UInt16; + dat @1 :Data; +} + struct ThermalData { cpu0 @0 :UInt16; cpu1 @1 :UInt16; @@ -1639,5 +1644,7 @@ struct Event { boot @60 :Boot; liveParameters @61 :LiveParametersData; liveMapData @62 :LiveMapData; + flexRay @63 :List(FlexRayData); + sendFlexRay @64 :List(FlexRayData); } } diff --git a/common/params.py b/common/params.py index 3981a341f4e28c..9a20a4221cd151 100755 --- a/common/params.py +++ b/common/params.py @@ -69,6 +69,9 @@ class UnknownKeyName(Exception): # written: controlsd # read: radard "CarParams": TxType.CLEAR_ON_CAR_START, +# written: controlsd??? +# read: flexrayd + "FlexRayParams": TxType.CLEAR_ON_CAR_START, "Passive": TxType.PERSISTENT, "DoUninstall": TxType.CLEAR_ON_MANAGER_START, diff --git a/flexray_adapter/.gitignore b/flexray_adapter/.gitignore new file mode 100644 index 00000000000000..57f1cb2a7a1855 --- /dev/null +++ b/flexray_adapter/.gitignore @@ -0,0 +1 @@ +/.idea/ \ No newline at end of file diff --git a/flexray_adapter/README.md b/flexray_adapter/README.md new file mode 100644 index 00000000000000..55dcba0ce131e0 --- /dev/null +++ b/flexray_adapter/README.md @@ -0,0 +1,155 @@ +![](https://i.ibb.co/09tj5Q6/all.jpg) + +FlexRay adapter for [openpilot](http://github.com/commaai/openpilot) +====== + +Features +------ + +- FlexRay driver for MPC5748G +- FlexRay adapter for [EON Dashcam DevKit](https://comma.ai/shop/products/EON-dashcam-devkit) and PC (Windows 7/10, Ubuntu), send & receive FlexRay frames over ethernet(TCP). +- Flexray boardd implementation for OpenPilot, forward FlexRay frames to ZMQ. +- A GUI application running on PC for facilitating FlexRay configuration. + - create/edit/load/export FlexRay configuration file. + - Validate/Auto-calculate FlexRay parameters according to the constraints defined in FlexRay spec 2.1 appendix A. + - Troubleshoot FlexRay configuration problems, view protocol status data on the board. + - Start/stop FlexRay driver. + - Change the FlexRay configuration on the adapter. + - Sniff on FlexRay bus, display received frames. + - Send frames, customize frame ID and payload content. + +Hardware Support +------ + +Right now the FlexRay adapter supports the MPC5748G chip, tested on [DEVKIT MPC5748G](https://www.nxp.com/products/processors-and-microcontrollers/power-architecture-processors/mpc5xxx-55xx-32-bit-mcus/ultra-reliable-mpc57xx-32-bit-automotive-and-industrial-microcontrollers-mcus/development-board-for-mpc5748g:DEVKIT-MPC5748G). + + +Directory structure +------ + . + └── flexray_adapter # NXP S32 Design Studio project root directory + └── Sources + ├── flexray_driver.c # FlexRay driver API code + ├── flexray_config.h # FlexRay configuration parameters definition + ├── flexray_state_machine.c # FlexRay state machine, control the FlexRay CC via FlexRay driver API + ├── tcp_interface.c # TCP interfacing implementation + ├── tcpip_stack.c # lwIP TCP/IP stack launching + └── packet.h # A packet based protocol for TCP interfacing + └── python + ├── flexray_config.py # FlexRay configuration file API + ├── tcp_interface.py # FlexRay TCP interfacing API + ├── gui.py # FlexRay test & configuration tool + └── test/ # Sample FlexRay configuration YAML files + .. + └── selfdrive + └── flexrayd + ├── flexrayd.c # FlexRay boardd + └── flexrayd_test.py # flexrayd test program + +How to compile +------ +- OS requirements + - Windows 10 + - Linux may also be OK but never get tested. +- Download and install [S32 Design Studio for Power Architecture 2017.R1 ](https://www.nxp.com/support/developer-resources/run-time-software/s32-design-studio-ide/s32-design-studio-ide-for-power-architecture-based-mcus:S32DS-PA?tab=Design_Tools_Tab) to default position( %SystemDrive%\NXP). A free account registration will be required. +- Install S32DS for Power Architecture 2017.R1 Update 7, make sure the MPC574xx SDK RTM 1.0.0 is installed: + 1. On the S32DS download page, find the Update 7, download and unzip to local folder. + 2. Launch S32 design studio, open "Help" menu, choose "Install new software...", then click "Add..." button to open Add Repository dialog, click "Local..." button, browse to the folder where Update 7 is unzipped, click "OK" button. + 3. Make sure "MPC74xx SDK RTM 1.0.0" is checked, then begin installation. + ![]( https://i.ibb.co/C9JMbYr/SDK-RTM-1-0-0.png) +- Create a workspace in S32DS, import flexray_adapter project into current workspace. +- Build the project. + +How to debug +------ +- Connect DEVKIT MPC5748G to computer via the USB OpenSDA port. +- Choose DEBUG_RAM configuration and build. +- Set the debugger to OpenSDA in debug configuration window. +- Start debugging. + +How to test +------ + +- ### Establish FlexRay communication between PC and EON + - Hardware preparation + - A PC running Windows 10 or Ubuntu Desktop. + - A EON running OpenPilot. + - A [Comma SMAYS](https://comma.ai/shop/products/comma-smays-adapter/) for EON interfacing. + - Two MPC5748G DEVKIT boards flashed using the output ELF file from compilation of the flexray_adapter S32S project. + - Connect all hardware together + - Connect the MPC5748 boards via the FlexRay port using a 1.25mm 2pin connector. + - Connect a MPC5748 board to EON via Comma SMAYS and an ethernet cable, set the IP address of ethernet adapter to 192.168.5.10. + - Connect the USB port of Comma SMAYS to PC for power supply. + - Connect the other MPC5748 board to PC via an ethernet cable, set the IP address of ethernet adapter to 192.168.5.10. + - Start FlexRay communication On EON + - Start test python script and flexrayd: + ```bash + root@localhost:/data/openpilot/selfdrive/flexrayd$ ./flexrayd_test.py + Loading FlexRay config file: ../../flexray_adapter/python/test/node1.yml... + Tx Static Slot ids: [1, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60] + Tx Dynamic Slot ids: [61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80] + Listening for FlexRay frames + Type a tx slot id to send a frame, 'q' to exit, 'h' to show tx slot ids: + ``` + ```bash + root@localhost:/data/openpilot/selfdrive/flexrayd$ ./flexrayd + flexrayd.cc: starting flexrayd + connecting + flexrayd.cc: waiting for flexray params + flexrayd.cc: got 892 bytes of flexray params + ``` + - Start FlexRay communication on PC + - Launch flexray_tool.py. + - Click "Join into FlexRay Network" button. + - From the dropdown list, choose node2.yml, click "Load selected file" button. + ![](https://i.ibb.co/wBjSVtS/Connect-To-Flex-Ray.png) + - Click "Connect" button + - After successful connection, flexray_tool GUI will show "POC status: normal active", and the number of sync frames will become 4. + ![](https://i.ibb.co/841NtCb/Flex-Ray-Tool.png) + - Send frame test + - Send frame on static slot id 1 on EON + ```bash + root@localhost:/data/openpilot/selfdrive/flexrayd$ ./flexrayd_test.py + Loading FlexRay config file: ../../flexray_adapter/python/test/node1.yml... + Tx Static Slot ids: [1, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60] + Tx Dynamic Slot ids: [61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 7 5, 76, 77, 78, 79, 80] + Listening for FlexRay frames + Type a tx slot id to send a frame, 'q' to exit, 'h' to show tx slot ids:1 + Start sending on slot id 1... + Type a tx slot id to send a frame, 'q' to exit, 'h' to show tx slot ids: + ``` + Inspect the frames on PC + ![](https://i.ibb.co/sJ80RRb/RxFrames.png) + - Send frame on static slot id 2 on PC + - Click "Send frame" button. + - Click the Checkbox before "static slot 2", fill the payload with some data, then click "Start sending" button. + ![](https://i.ibb.co/2jmMrBG/Send-Frame.png) + Inspect the frames on EON + ```bash + Frame 0 , ID: 2 , Payload Len: 64 ['0x55', '0x55', '0x55', '0x55', '0x55', '0x55', '0x55', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0'] + ``` + +Some thoughts on how to connect the adapter to car's FlexRay network +------ +- Capture the car's FlexRay traffic + - Find the FlexRay port where the LKAS camera is connected. + - Connect a oscilloscope(like [PicoScope](https://www.picotech.com/products/oscilloscope)) to the FlexRay BP or BM port. + - Start the car, capture a waveform. +- Estimate the FlexRay parameters + - Decode the FlexRay frame from the waveform using PicoScope software to get slot/frame parameters, such as gdPayloadLengthStatic. + - Analyze the waveform to estimate timing parameters, such as gdTSSTransmitter, gdMacroTick, gdCycle, etc. +- Connect test + - Use the estimated parameters to create a config file in flexray_tool. + - Connect FlexRay adapter to the car instead of the oscilloscope. + - Use the config file to join the FlexRay network. + + Reference Documents +------ +- [MPC5748G Reference Manual](https://www.nxp.com/docs/en/reference-manual/MPC5748GRM.pdf) +- [DEVKIT-MPC5478G Quick Start Guide](https://www.nxp.com/docs/en/quick-reference-guide/DEVKIT-MPC5748G-QSG.pdf) +- FlexRay Protocol Specification Version 2.1 Revision A + +Licensing +------ + +MIT license. diff --git a/flexray_adapter/__init__.py b/flexray_adapter/__init__.py new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/flexray_adapter/flexray_adapter/.cproject b/flexray_adapter/flexray_adapter/.cproject new file mode 100644 index 00000000000000..1af793412f06db --- /dev/null +++ b/flexray_adapter/flexray_adapter/.cproject @@ -0,0 +1,659 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/flexray_adapter/flexray_adapter/.flexray_adapter.g_c b/flexray_adapter/flexray_adapter/.flexray_adapter.g_c new file mode 100644 index 00000000000000..2a5f61f95dbe82 --- /dev/null +++ b/flexray_adapter/flexray_adapter/.flexray_adapter.g_c @@ -0,0 +1,1119 @@ + + + + flexray_adapter + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\ + main + Sources\ + ..\Generated_Code\ + Documentation\ + + + MPC5748G_176 + + false + false + + + Generated_Code\FreeRTOSConfig.h + Generated_Code\lwippools.h + Generated_Code\lwipopts.h + Generated_Code\lwipcfg.h + + 1299670528 + 1297127240 + 1297659466 + 1297127240 + 4 + 4 + 4 + 4 + + SDK\platform\devices\devassert.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\devices\devassert.h + SDK\platform\devices\status.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\devices\status.h + SDK\platform\devices\device_registers.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\devices\device_registers.h + SDK\platform\devices\callbacks.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\devices\callbacks.h + SDK\platform\devices\common\s32_core_e200.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\devices\common\s32_core_e200.h + SDK\platform\devices\startup.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\devices\startup.h + SDK\platform\devices\startup.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\devices\startup.c + SDK\platform\devices\MPC5748G\startup\system_MPC5748G.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\devices\MPC5748G\startup\system_MPC5748G.h + SDK\platform\devices\MPC5748G\startup\system_MPC5748G.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\devices\MPC5748G\startup\system_MPC5748G.c + SDK\platform\devices\MPC5748G\include\MPC5748G_features.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\devices\MPC5748G\include\MPC5748G_features.h + SDK\platform\devices\MPC5748G\include\MPC5748G.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\devices\MPC5748G\include\MPC5748G.h + SDK\platform\drivers\src\edma\edma_driver.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\edma\edma_driver.c + SDK\platform\drivers\src\edma\edma_hw_access.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\edma\edma_hw_access.c + SDK\platform\drivers\src\edma\edma_irq.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\edma\edma_irq.c + SDK\platform\drivers\src\edma\edma_hw_access.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\edma\edma_hw_access.h + SDK\platform\drivers\src\edma\edma_irq.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\edma\edma_irq.h + SDK\platform\drivers\inc\edma_driver.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\inc\edma_driver.h + SDK\platform\drivers\src\linflexd\linflexd_uart_driver.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\linflexd\linflexd_uart_driver.c + SDK\platform\drivers\src\linflexd\linflexd_uart_irq.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\linflexd\linflexd_uart_irq.c + SDK\platform\drivers\inc\linflexd_uart_driver.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\inc\linflexd_uart_driver.h + SDK\platform\drivers\src\linflexd\linflexd_hw_access.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\linflexd\linflexd_hw_access.h + SDK\platform\drivers\src\linflexd\linflexd_uart_irq.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\linflexd\linflexd_uart_irq.h + SDK\middleware\tcpip\lwip\src\include\lwip\api.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\api.h + SDK\middleware\tcpip\lwip\src\include\lwip\arch.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\arch.h + SDK\middleware\tcpip\lwip\src\include\lwip\autoip.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\autoip.h + SDK\middleware\tcpip\lwip\src\include\lwip\debug.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\debug.h + SDK\middleware\tcpip\lwip\src\include\lwip\def.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\def.h + SDK\middleware\tcpip\lwip\src\include\lwip\dhcp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\dhcp.h + SDK\middleware\tcpip\lwip\src\include\lwip\dhcp6.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\dhcp6.h + SDK\middleware\tcpip\lwip\src\include\lwip\dns.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\dns.h + SDK\middleware\tcpip\lwip\src\include\lwip\err.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\err.h + SDK\middleware\tcpip\lwip\src\include\lwip\errno.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\errno.h + SDK\middleware\tcpip\lwip\src\include\lwip\etharp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\etharp.h + SDK\middleware\tcpip\lwip\src\include\lwip\ethip6.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\ethip6.h + SDK\middleware\tcpip\lwip\src\include\lwip\icmp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\icmp.h + SDK\middleware\tcpip\lwip\src\include\lwip\icmp6.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\icmp6.h + SDK\middleware\tcpip\lwip\src\include\lwip\igmp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\igmp.h + SDK\middleware\tcpip\lwip\src\include\lwip\inet.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\inet.h + SDK\middleware\tcpip\lwip\src\include\lwip\inet_chksum.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\inet_chksum.h + SDK\middleware\tcpip\lwip\src\include\lwip\init.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\init.h + SDK\middleware\tcpip\lwip\src\include\lwip\ip.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\ip.h + SDK\middleware\tcpip\lwip\src\include\lwip\ip4.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\ip4.h + SDK\middleware\tcpip\lwip\src\include\lwip\ip4_addr.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\ip4_addr.h + SDK\middleware\tcpip\lwip\src\include\lwip\ip4_frag.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\ip4_frag.h + SDK\middleware\tcpip\lwip\src\include\lwip\ip6.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\ip6.h + SDK\middleware\tcpip\lwip\src\include\lwip\ip6_addr.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\ip6_addr.h + SDK\middleware\tcpip\lwip\src\include\lwip\ip6_frag.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\ip6_frag.h + SDK\middleware\tcpip\lwip\src\include\lwip\ip_addr.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\ip_addr.h + SDK\middleware\tcpip\lwip\src\include\lwip\mem.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\mem.h + SDK\middleware\tcpip\lwip\src\include\lwip\memp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\memp.h + SDK\middleware\tcpip\lwip\src\include\lwip\mld6.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\mld6.h + SDK\middleware\tcpip\lwip\src\include\lwip\nd6.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\nd6.h + SDK\middleware\tcpip\lwip\src\include\lwip\netbuf.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\netbuf.h + SDK\middleware\tcpip\lwip\src\include\lwip\netdb.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\netdb.h + SDK\middleware\tcpip\lwip\src\include\lwip\netif.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\netif.h + SDK\middleware\tcpip\lwip\src\include\lwip\netifapi.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\netifapi.h + SDK\middleware\tcpip\lwip\src\include\lwip\opt.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\opt.h + SDK\middleware\tcpip\lwip\src\include\lwip\pbuf.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\pbuf.h + SDK\middleware\tcpip\lwip\src\include\lwip\raw.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\raw.h + SDK\middleware\tcpip\lwip\src\include\lwip\sio.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\sio.h + SDK\middleware\tcpip\lwip\src\include\lwip\snmp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\snmp.h + SDK\middleware\tcpip\lwip\src\include\lwip\sockets.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\sockets.h + SDK\middleware\tcpip\lwip\src\include\lwip\stats.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\stats.h + SDK\middleware\tcpip\lwip\src\include\lwip\sys.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\sys.h + SDK\middleware\tcpip\lwip\src\include\lwip\tcp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\tcp.h + SDK\middleware\tcpip\lwip\src\include\lwip\tcpip.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\tcpip.h + SDK\middleware\tcpip\lwip\src\include\lwip\timeouts.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\timeouts.h + SDK\middleware\tcpip\lwip\src\include\lwip\udp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\udp.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\FILES=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\FILES + SDK\middleware\tcpip\lwip\src\include\lwip\apps\fs.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\fs.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\httpd.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\httpd.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\httpd_opts.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\httpd_opts.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\lwiperf.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\lwiperf.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\mdns.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\mdns.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\mdns_opts.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\mdns_opts.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\mdns_priv.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\mdns_priv.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\mqtt.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\mqtt.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\mqtt_opts.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\mqtt_opts.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\netbiosns.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\netbiosns.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\netbiosns_opts.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\netbiosns_opts.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\snmp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\snmp.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\snmpv3.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\snmpv3.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\snmp_core.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\snmp_core.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\snmp_mib2.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\snmp_mib2.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\snmp_opts.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\snmp_opts.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\snmp_scalar.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\snmp_scalar.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\snmp_table.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\snmp_table.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\snmp_threadsync.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\snmp_threadsync.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\sntp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\sntp.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\sntp_opts.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\sntp_opts.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\tftp_opts.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\tftp_opts.h + SDK\middleware\tcpip\lwip\src\include\lwip\apps\tftp_server.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\apps\tftp_server.h + SDK\middleware\tcpip\lwip\src\include\lwip\priv\api_msg.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\priv\api_msg.h + SDK\middleware\tcpip\lwip\src\include\lwip\priv\memp_priv.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\priv\memp_priv.h + SDK\middleware\tcpip\lwip\src\include\lwip\priv\memp_std.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\priv\memp_std.h + SDK\middleware\tcpip\lwip\src\include\lwip\priv\nd6_priv.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\priv\nd6_priv.h + SDK\middleware\tcpip\lwip\src\include\lwip\priv\tcpip_priv.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\priv\tcpip_priv.h + SDK\middleware\tcpip\lwip\src\include\lwip\priv\tcp_priv.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\priv\tcp_priv.h + SDK\middleware\tcpip\lwip\src\include\lwip\prot\autoip.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\prot\autoip.h + SDK\middleware\tcpip\lwip\src\include\lwip\prot\dhcp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\prot\dhcp.h + SDK\middleware\tcpip\lwip\src\include\lwip\prot\dns.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\prot\dns.h + SDK\middleware\tcpip\lwip\src\include\lwip\prot\etharp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\prot\etharp.h + SDK\middleware\tcpip\lwip\src\include\lwip\prot\ethernet.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\prot\ethernet.h + SDK\middleware\tcpip\lwip\src\include\lwip\prot\icmp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\prot\icmp.h + SDK\middleware\tcpip\lwip\src\include\lwip\prot\icmp6.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\prot\icmp6.h + SDK\middleware\tcpip\lwip\src\include\lwip\prot\igmp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\prot\igmp.h + SDK\middleware\tcpip\lwip\src\include\lwip\prot\ip.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\prot\ip.h + SDK\middleware\tcpip\lwip\src\include\lwip\prot\ip4.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\prot\ip4.h + SDK\middleware\tcpip\lwip\src\include\lwip\prot\ip6.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\prot\ip6.h + SDK\middleware\tcpip\lwip\src\include\lwip\prot\mld6.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\prot\mld6.h + SDK\middleware\tcpip\lwip\src\include\lwip\prot\nd6.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\prot\nd6.h + SDK\middleware\tcpip\lwip\src\include\lwip\prot\tcp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\prot\tcp.h + SDK\middleware\tcpip\lwip\src\include\lwip\prot\udp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\lwip\prot\udp.h + SDK\middleware\tcpip\lwip\src\include\netif\etharp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\etharp.h + SDK\middleware\tcpip\lwip\src\include\netif\ethernet.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ethernet.h + SDK\middleware\tcpip\lwip\src\include\netif\lowpan6.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\lowpan6.h + SDK\middleware\tcpip\lwip\src\include\netif\lowpan6_opts.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\lowpan6_opts.h + SDK\middleware\tcpip\lwip\src\include\netif\slipif.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\slipif.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\ccp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\ccp.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\chap-md5.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\chap-md5.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\chap-new.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\chap-new.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\chap_ms.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\chap_ms.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\eap.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\eap.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\ecp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\ecp.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\eui64.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\eui64.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\fsm.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\fsm.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\ipcp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\ipcp.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\ipv6cp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\ipv6cp.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\lcp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\lcp.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\magic.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\magic.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\mppe.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\mppe.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\ppp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\ppp.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\pppapi.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\pppapi.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\pppcrypt.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\pppcrypt.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\pppdebug.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\pppdebug.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\pppoe.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\pppoe.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\pppol2tp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\pppol2tp.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\pppos.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\pppos.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\ppp_impl.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\ppp_impl.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\ppp_opts.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\ppp_opts.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\upap.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\upap.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\vj.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\vj.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\polarssl\arc4.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\polarssl\arc4.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\polarssl\des.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\polarssl\des.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\polarssl\md4.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\polarssl\md4.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\polarssl\md5.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\polarssl\md5.h + SDK\middleware\tcpip\lwip\src\include\netif\ppp\polarssl\sha1.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\netif\ppp\polarssl\sha1.h + SDK\middleware\tcpip\lwip\src\include\posix\errno.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\posix\errno.h + SDK\middleware\tcpip\lwip\src\include\posix\netdb.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\posix\netdb.h + SDK\middleware\tcpip\lwip\src\include\posix\sys\socket.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\include\posix\sys\socket.h + SDK\middleware\tcpip\lwip\src\core\def.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\def.c + SDK\middleware\tcpip\lwip\src\core\dns.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\dns.c + SDK\middleware\tcpip\lwip\src\core\inet_chksum.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\inet_chksum.c + SDK\middleware\tcpip\lwip\src\core\init.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\init.c + SDK\middleware\tcpip\lwip\src\core\ip.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\ip.c + SDK\middleware\tcpip\lwip\src\core\mem.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\mem.c + SDK\middleware\tcpip\lwip\src\core\memp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\memp.c + SDK\middleware\tcpip\lwip\src\core\netif.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\netif.c + SDK\middleware\tcpip\lwip\src\core\pbuf.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\pbuf.c + SDK\middleware\tcpip\lwip\src\core\raw.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\raw.c + SDK\middleware\tcpip\lwip\src\core\stats.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\stats.c + SDK\middleware\tcpip\lwip\src\core\sys.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\sys.c + SDK\middleware\tcpip\lwip\src\core\tcp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\tcp.c + SDK\middleware\tcpip\lwip\src\core\tcp_in.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\tcp_in.c + SDK\middleware\tcpip\lwip\src\core\tcp_out.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\tcp_out.c + SDK\middleware\tcpip\lwip\src\core\timeouts.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\timeouts.c + SDK\middleware\tcpip\lwip\src\core\udp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\udp.c + SDK\middleware\tcpip\lwip\src\netif\ethernet.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ethernet.c + SDK\middleware\tcpip\lwip\src\netif\ethernetif.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ethernetif.c + SDK\middleware\tcpip\lwip\src\netif\FILES=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\FILES + SDK\middleware\tcpip\lwip\src\netif\lowpan6.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\lowpan6.c + SDK\middleware\tcpip\lwip\src\netif\slipif.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\slipif.c + SDK\middleware\tcpip\lwip\src\netif\ppp\auth.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\auth.c + SDK\middleware\tcpip\lwip\src\netif\ppp\ccp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\ccp.c + SDK\middleware\tcpip\lwip\src\netif\ppp\chap-md5.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\chap-md5.c + SDK\middleware\tcpip\lwip\src\netif\ppp\chap-new.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\chap-new.c + SDK\middleware\tcpip\lwip\src\netif\ppp\chap_ms.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\chap_ms.c + SDK\middleware\tcpip\lwip\src\netif\ppp\demand.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\demand.c + SDK\middleware\tcpip\lwip\src\netif\ppp\eap.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\eap.c + SDK\middleware\tcpip\lwip\src\netif\ppp\ecp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\ecp.c + SDK\middleware\tcpip\lwip\src\netif\ppp\eui64.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\eui64.c + SDK\middleware\tcpip\lwip\src\netif\ppp\fsm.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\fsm.c + SDK\middleware\tcpip\lwip\src\netif\ppp\ipcp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\ipcp.c + SDK\middleware\tcpip\lwip\src\netif\ppp\ipv6cp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\ipv6cp.c + SDK\middleware\tcpip\lwip\src\netif\ppp\lcp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\lcp.c + SDK\middleware\tcpip\lwip\src\netif\ppp\magic.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\magic.c + SDK\middleware\tcpip\lwip\src\netif\ppp\mppe.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\mppe.c + SDK\middleware\tcpip\lwip\src\netif\ppp\multilink.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\multilink.c + SDK\middleware\tcpip\lwip\src\netif\ppp\ppp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\ppp.c + SDK\middleware\tcpip\lwip\src\netif\ppp\pppapi.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\pppapi.c + SDK\middleware\tcpip\lwip\src\netif\ppp\pppcrypt.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\pppcrypt.c + SDK\middleware\tcpip\lwip\src\netif\ppp\PPPD_FOLLOWUP=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\PPPD_FOLLOWUP + SDK\middleware\tcpip\lwip\src\netif\ppp\pppoe.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\pppoe.c + SDK\middleware\tcpip\lwip\src\netif\ppp\pppol2tp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\pppol2tp.c + SDK\middleware\tcpip\lwip\src\netif\ppp\pppos.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\pppos.c + SDK\middleware\tcpip\lwip\src\netif\ppp\upap.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\upap.c + SDK\middleware\tcpip\lwip\src\netif\ppp\utils.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\utils.c + SDK\middleware\tcpip\lwip\src\netif\ppp\vj.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\vj.c + SDK\middleware\tcpip\lwip\src\netif\ppp\polarssl\arc4.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\polarssl\arc4.c + SDK\middleware\tcpip\lwip\src\netif\ppp\polarssl\des.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\polarssl\des.c + SDK\middleware\tcpip\lwip\src\netif\ppp\polarssl\md4.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\polarssl\md4.c + SDK\middleware\tcpip\lwip\src\netif\ppp\polarssl\md5.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\polarssl\md5.c + SDK\middleware\tcpip\lwip\src\netif\ppp\polarssl\README=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\polarssl\README + SDK\middleware\tcpip\lwip\src\netif\ppp\polarssl\sha1.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\netif\ppp\polarssl\sha1.c + SDK\middleware\tcpip\tcpip_stack\ports\OS\arch\sys_arch.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\tcpip_stack\ports\OS\arch\sys_arch.h + SDK\middleware\tcpip\tcpip_stack\addons\tcp_isn\tcp_isn.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\tcpip_stack\addons\tcp_isn\tcp_isn.c + SDK\middleware\tcpip\tcpip_stack\addons\tcp_isn\tcp_isn.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\tcpip_stack\addons\tcp_isn\tcp_isn.h + SDK\middleware\tcpip\tcpip_stack\ports\OS\sys_arch.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\tcpip_stack\ports\OS\sys_arch.c + SDK\middleware\tcpip\tcpip_stack\ports\platform\MPC5748G\make\gcc\arch\cc.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\tcpip_stack\ports\platform\MPC5748G\make\gcc\arch\cc.h + SDK\middleware\tcpip\tcpip_stack\ports\platform\MPC5748G\make\gcc\arch\perf.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\tcpip_stack\ports\platform\MPC5748G\make\gcc\arch\perf.h + SDK\platform\drivers\src\enet\enet_driver.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\enet\enet_driver.c + SDK\platform\drivers\src\enet\enet_irq.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\enet\enet_irq.c + SDK\platform\drivers\src\enet\enet_hw_access.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\enet\enet_hw_access.c + SDK\platform\drivers\src\enet\enet_hw_access.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\enet\enet_hw_access.h + SDK\platform\drivers\inc\enet_driver.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\inc\enet_driver.h + SDK\middleware\tcpip\lwip\src\core\ipv4\autoip.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\ipv4\autoip.c + SDK\middleware\tcpip\lwip\src\core\ipv4\dhcp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\ipv4\dhcp.c + SDK\middleware\tcpip\lwip\src\core\ipv4\etharp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\ipv4\etharp.c + SDK\middleware\tcpip\lwip\src\core\ipv4\icmp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\ipv4\icmp.c + SDK\middleware\tcpip\lwip\src\core\ipv4\igmp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\ipv4\igmp.c + SDK\middleware\tcpip\lwip\src\core\ipv4\ip4.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\ipv4\ip4.c + SDK\middleware\tcpip\lwip\src\core\ipv4\ip4_addr.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\ipv4\ip4_addr.c + SDK\middleware\tcpip\lwip\src\core\ipv4\ip4_frag.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\core\ipv4\ip4_frag.c + SDK\middleware\tcpip\tcpip_stack\ports\netif\enetif\enetif.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\tcpip_stack\ports\netif\enetif\enetif.h + SDK\middleware\tcpip\tcpip_stack\ports\netif\enetif\enetif.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\tcpip_stack\ports\netif\enetif\enetif.c + SDK\middleware\tcpip\tcpip_stack\ports\netif\enetif\Filelists.mk=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\tcpip_stack\ports\netif\enetif\Filelists.mk + SDK\middleware\tcpip\tcpip_stack\demo\test.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\tcpip_stack\demo\test.c + SDK\middleware\tcpip\lwip\src\api\api_lib.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\api\api_lib.c + SDK\middleware\tcpip\lwip\src\api\api_msg.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\api\api_msg.c + SDK\middleware\tcpip\lwip\src\api\err.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\api\err.c + SDK\middleware\tcpip\lwip\src\api\netbuf.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\api\netbuf.c + SDK\middleware\tcpip\lwip\src\api\netdb.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\api\netdb.c + SDK\middleware\tcpip\lwip\src\api\netifapi.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\api\netifapi.c + SDK\middleware\tcpip\lwip\src\api\sockets.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\api\sockets.c + SDK\middleware\tcpip\lwip\src\api\tcpip.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\api\tcpip.c + SDK\middleware\tcpip\lwip\src\apps\mdns\mdns.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\mdns\mdns.c + SDK\middleware\tcpip\lwip\src\apps\mqtt\mqtt.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\mqtt\mqtt.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmpv3.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmpv3.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmpv3_dummy.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmpv3_dummy.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmpv3_mbedtls.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmpv3_mbedtls.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmpv3_priv.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmpv3_priv.h + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_asn1.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_asn1.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_asn1.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_asn1.h + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_core.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_core.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_core_priv.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_core_priv.h + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_mib2.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_mib2.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_mib2_icmp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_mib2_icmp.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_mib2_interfaces.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_mib2_interfaces.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_mib2_ip.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_mib2_ip.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_mib2_snmp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_mib2_snmp.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_mib2_system.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_mib2_system.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_mib2_tcp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_mib2_tcp.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_mib2_udp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_mib2_udp.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_msg.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_msg.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_msg.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_msg.h + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_netconn.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_netconn.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_pbuf_stream.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_pbuf_stream.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_pbuf_stream.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_pbuf_stream.h + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_raw.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_raw.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_scalar.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_scalar.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_table.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_table.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_threadsync.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_threadsync.c + SDK\middleware\tcpip\lwip\src\apps\snmp\snmp_traps.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\snmp\snmp_traps.c + SDK\middleware\tcpip\lwip\src\apps\tftp\tftp_server.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\lwip\src\apps\tftp\tftp_server.c + SDK\middleware\tcpip\tcpip_stack\apps\smtp\smtp.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\tcpip_stack\apps\smtp\smtp.c + SDK\middleware\tcpip\tcpip_stack\apps\smtp\smtp.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\tcpip_stack\apps\smtp\smtp.h + SDK\middleware\tcpip\tcpip_stack\apps\snmp_private_mib\lwip_prvmib.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\tcpip_stack\apps\snmp_private_mib\lwip_prvmib.c + SDK\middleware\tcpip\tcpip_stack\apps\snmp_private_mib\private_mib.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\middleware\tcpip\tcpip_stack\apps\snmp_private_mib\private_mib.h + SDK\platform\drivers\src\pins\pins_driver.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\pins\pins_driver.c + SDK\platform\drivers\src\pins\pins_gpio_hw_access.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\pins\pins_gpio_hw_access.h + SDK\platform\drivers\inc\pins_driver.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\inc\pins_driver.h + SDK\platform\drivers\src\pins\pins_siul2_hw_access.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\pins\pins_siul2_hw_access.c + SDK\platform\drivers\src\pins\pins_siul2_hw_access.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\pins\pins_siul2_hw_access.h + SDK\rtos\FreeRTOS_C55\Source\croutine.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\croutine.c + SDK\rtos\FreeRTOS_C55\Source\event_groups.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\event_groups.c + SDK\rtos\FreeRTOS_C55\Source\list.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\list.c + SDK\rtos\FreeRTOS_C55\Source\queue.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\queue.c + SDK\rtos\FreeRTOS_C55\Source\tasks.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\tasks.c + SDK\rtos\FreeRTOS_C55\Source\timers.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\timers.c + SDK\rtos\FreeRTOS_C55\Source\portable\GCC\PowerPC_Z4\port.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\portable\GCC\PowerPC_Z4\port.c + SDK\rtos\FreeRTOS_C55\Source\portable\GCC\PowerPC_Z4\porttimer.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\portable\GCC\PowerPC_Z4\porttimer.c + SDK\rtos\FreeRTOS_C55\Source\portable\GCC\PowerPC_Z4\cpu_defines.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\portable\GCC\PowerPC_Z4\cpu_defines.h + SDK\rtos\FreeRTOS_C55\Source\portable\GCC\PowerPC_Z4\portmacro.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\portable\GCC\PowerPC_Z4\portmacro.h + SDK\rtos\FreeRTOS_C55\Source\portable\GCC\PowerPC_Z4\portasm.s=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\portable\GCC\PowerPC_Z4\portasm.s + SDK\rtos\FreeRTOS_C55\Source\include\croutine.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\include\croutine.h + SDK\rtos\FreeRTOS_C55\Source\include\deprecated_definitions.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\include\deprecated_definitions.h + SDK\rtos\FreeRTOS_C55\Source\include\event_groups.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\include\event_groups.h + SDK\rtos\FreeRTOS_C55\Source\include\FreeRTOS.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\include\FreeRTOS.h + SDK\rtos\FreeRTOS_C55\Source\include\list.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\include\list.h + SDK\rtos\FreeRTOS_C55\Source\include\mpu_prototypes.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\include\mpu_prototypes.h + SDK\rtos\FreeRTOS_C55\Source\include\mpu_wrappers.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\include\mpu_wrappers.h + SDK\rtos\FreeRTOS_C55\Source\include\portable.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\include\portable.h + SDK\rtos\FreeRTOS_C55\Source\include\projdefs.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\include\projdefs.h + SDK\rtos\FreeRTOS_C55\Source\include\queue.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\include\queue.h + SDK\rtos\FreeRTOS_C55\Source\include\semphr.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\include\semphr.h + SDK\rtos\FreeRTOS_C55\Source\include\StackMacros.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\include\StackMacros.h + SDK\rtos\FreeRTOS_C55\Source\include\task.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\include\task.h + SDK\rtos\FreeRTOS_C55\Source\include\timers.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\include\timers.h + SDK\rtos\FreeRTOS_C55\Source\portable\MemMang\heap_4.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\FreeRTOS_C55\Source\portable\MemMang\heap_4.c + SDK\rtos\osif\osif.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\osif\osif.h + SDK\rtos\osif\osif_freertos.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\rtos\osif\osif_freertos.c + SDK\platform\drivers\src\clock\clock_manager.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\clock\clock_manager.c + SDK\platform\drivers\src\clock\MPC57xx\clock_MPC57xx.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\clock\MPC57xx\clock_MPC57xx.c + SDK\platform\drivers\src\clock\MPC57xx\cgmcs_hw_access.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\clock\MPC57xx\cgmcs_hw_access.h + SDK\platform\drivers\src\clock\MPC57xx\cgm_hw_access.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\clock\MPC57xx\cgm_hw_access.h + SDK\platform\drivers\src\clock\MPC57xx\clock_MPC57xx.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\clock\MPC57xx\clock_MPC57xx.h + SDK\platform\drivers\src\clock\MPC57xx\mc_me_hw_access.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\clock\MPC57xx\mc_me_hw_access.h + SDK\platform\drivers\inc\clock_manager.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\inc\clock_manager.h + SDK\platform\drivers\src\interrupt\interrupt_manager_MPC57xx.c=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\src\interrupt\interrupt_manager_MPC57xx.c + SDK\platform\drivers\inc\interrupt_manager.h=C:\NXP\S32DS_Power_v2017.R1\eclipse\..\S32DS\S32_SDK_MPC574xx_RTM_1.0.0\platform\drivers\inc\interrupt_manager.h + + + Events + + + FreeRTOS_vApplicationStackOverflowHook + + + clockMan1 + Cpu + dmaController1 + Events + FreeRTOS + linflexd_uart1 + pin_mux + + + + FreeRTOS + pin_mux + clockMan1 + linflexd_uart1 + dmaController1 + + + + GNUC + 164 + + + true + Cpu + 01.197 + 01.00 + Events + 1297127240 + 1297127240 + -1 + 3 + true + true + true + 1 + 0 + Cpu_OnEvent + interrupts disabled + false + false + false + 11 + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\platform\devices\MPC5748G\include\MPC5748G.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\platform\devices\MPC5748G\include\MPC5748G_features.h + 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D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\core\udp.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\core\timeouts.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\core\tcp_out.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\core\tcp_in.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\core\tcp.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\core\sys.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\core\stats.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\core\raw.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\core\pbuf.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\core\netif.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\core\memp.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\core\mem.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\core\ip.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\core\init.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\core\inet_chksum.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\core\dns.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\core\def.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\posix\sys\socket.h + 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D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\upap.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\ppp_opts.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\ppp_impl.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\pppos.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\pppol2tp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\pppoe.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\pppdebug.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\pppcrypt.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\pppapi.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\ppp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\mppe.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\magic.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\lcp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\ipv6cp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\ipcp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\fsm.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\eui64.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\ecp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\eap.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\chap_ms.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\chap-new.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\chap-md5.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ppp\ccp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\slipif.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\lowpan6_opts.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\lowpan6.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\ethernet.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\netif\etharp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\prot\udp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\prot\tcp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\prot\nd6.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\prot\mld6.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\prot\ip6.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\prot\ip4.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\prot\ip.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\prot\igmp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\prot\icmp6.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\prot\icmp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\prot\ethernet.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\prot\etharp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\prot\dns.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\prot\dhcp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\prot\autoip.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\priv\tcp_priv.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\priv\tcpip_priv.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\priv\nd6_priv.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\priv\memp_std.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\priv\memp_priv.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\priv\api_msg.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\tftp_server.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\tftp_opts.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\sntp_opts.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\sntp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\snmp_threadsync.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\snmp_table.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\snmp_scalar.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\snmp_opts.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\snmp_mib2.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\snmp_core.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\snmpv3.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\snmp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\netbiosns_opts.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\netbiosns.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\mqtt_opts.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\mqtt.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\mdns_priv.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\mdns_opts.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\mdns.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\lwiperf.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\httpd_opts.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\httpd.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\fs.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\apps\FILES + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\udp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\timeouts.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\tcpip.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\tcp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\sys.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\stats.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\sockets.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\snmp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\sio.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\raw.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\pbuf.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\opt.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\netifapi.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\netif.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\netdb.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\netbuf.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\nd6.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\mld6.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\memp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\mem.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\ip_addr.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\ip6_frag.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\ip6_addr.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\ip6.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\ip4_frag.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\ip4_addr.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\ip4.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\ip.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\init.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\inet_chksum.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\inet.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\igmp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\icmp6.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\icmp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\ethip6.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\etharp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\errno.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\err.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\dns.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\dhcp6.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\dhcp.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\def.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\debug.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\autoip.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\arch.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\middleware\tcpip\lwip\src\include\lwip\api.h + + + true + linflexd_uart1 + SDK_MPC574x_06 + 01.00 + + 1297127240 + 1297127240 + -1 + 17 + true + true + true + true + true + true + true + true + true + true + true + true + true + true + true + true + true + 0 + false + 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D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\platform\drivers\inc\edma_driver.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\platform\drivers\src\edma\edma_irq.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\platform\drivers\src\edma\edma_hw_access.h + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\platform\drivers\src\edma\edma_irq.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\platform\drivers\src\edma\edma_hw_access.c + D:\nanami\servers\mpc5748g\flexray_adapter\flexray_adapter\SDK\platform\drivers\src\edma\edma_driver.c + + + Drivers\C55\StaticSdk_C55.drv=1291554549 + Drivers\interrupt_manager.src=-1 + Drivers\osifcommon\osif.drv=-1 + Drivers\C55\StaticSdk_C55_V4.drv=1291554549 + Beans\_SDK\SdkOptions.chg=1291554428 + Drivers\Common\EBGNSupport\StringLib.prg=1291554550 + Drivers\linflexd_uart.src=-1 + Drivers\PEx_C55.src=1291554549 + Drivers\Common\HeaderFreescale.C=1291554550 + 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Drivers\Common\InitReg16Block.prg=1291554550 + + + diff --git a/flexray_adapter/flexray_adapter/.flexray_adapter.g_x b/flexray_adapter/flexray_adapter/.flexray_adapter.g_x new file mode 100644 index 00000000000000..fb810ba0f4b7eb --- /dev/null +++ b/flexray_adapter/flexray_adapter/.flexray_adapter.g_x @@ -0,0 +1,376 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 33 + \ No newline at end of file diff --git a/flexray_adapter/flexray_adapter/.gitignore b/flexray_adapter/flexray_adapter/.gitignore new file mode 100644 index 00000000000000..c6fca11dba57d6 --- /dev/null +++ b/flexray_adapter/flexray_adapter/.gitignore @@ -0,0 +1,3 @@ +/Debug_RAM/ +/Debug/ +/Release/ diff --git a/flexray_adapter/flexray_adapter/.project b/flexray_adapter/flexray_adapter/.project new file mode 100644 index 00000000000000..17e2324da4bcc2 --- /dev/null +++ b/flexray_adapter/flexray_adapter/.project @@ -0,0 +1,1617 @@ + + + flexray_adapter + + + + + + + com.freescale.processorexpert.core.expertprojectbuilder + auto,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.freescale.processorexpert.core.expertprojectnature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + 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+ + + SDK/middleware/tcpip/lwip/src/include/lwip/prot/mld6.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/lwip/prot/mld6.h + + + SDK/middleware/tcpip/lwip/src/include/lwip/prot/nd6.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/lwip/prot/nd6.h + + + SDK/middleware/tcpip/lwip/src/include/lwip/prot/tcp.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/lwip/prot/tcp.h + + + SDK/middleware/tcpip/lwip/src/include/lwip/prot/udp.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/lwip/prot/udp.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/ccp.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/ccp.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/chap-md5.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/chap-md5.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/chap-new.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/chap-new.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/chap_ms.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/chap_ms.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/eap.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/eap.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/ecp.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/ecp.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/eui64.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/eui64.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/fsm.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/fsm.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/ipcp.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/ipcp.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/ipv6cp.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/ipv6cp.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/lcp.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/lcp.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/magic.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/magic.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/mppe.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/mppe.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/ppp.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/ppp.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/ppp_impl.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/ppp_impl.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/ppp_opts.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/ppp_opts.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/pppapi.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/pppapi.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/pppcrypt.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/pppcrypt.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/pppdebug.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/pppdebug.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/pppoe.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/pppoe.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/pppol2tp.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/pppol2tp.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/pppos.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/pppos.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/upap.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/upap.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/vj.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/vj.h + + + SDK/middleware/tcpip/lwip/src/include/posix/sys/socket.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/posix/sys/socket.h + + + SDK/middleware/tcpip/lwip/src/netif/ppp/polarssl/README + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/netif/ppp/polarssl/README + + + SDK/middleware/tcpip/lwip/src/netif/ppp/polarssl/arc4.c + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/netif/ppp/polarssl/arc4.c + + + SDK/middleware/tcpip/lwip/src/netif/ppp/polarssl/des.c + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/netif/ppp/polarssl/des.c + + + SDK/middleware/tcpip/lwip/src/netif/ppp/polarssl/md4.c + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/netif/ppp/polarssl/md4.c + + + SDK/middleware/tcpip/lwip/src/netif/ppp/polarssl/md5.c + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/netif/ppp/polarssl/md5.c + + + SDK/middleware/tcpip/lwip/src/netif/ppp/polarssl/sha1.c + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/netif/ppp/polarssl/sha1.c + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/polarssl/arc4.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/polarssl/arc4.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/polarssl/des.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/polarssl/des.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/polarssl/md4.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/polarssl/md4.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/polarssl/md5.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/polarssl/md5.h + + + SDK/middleware/tcpip/lwip/src/include/netif/ppp/polarssl/sha1.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/lwip/src/include/netif/ppp/polarssl/sha1.h + + + SDK/middleware/tcpip/tcpip_stack/ports/platform/MPC5748G/make/gcc/arch/cc.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/tcpip_stack/ports/platform/MPC5748G/make/gcc/arch/cc.h + + + SDK/middleware/tcpip/tcpip_stack/ports/platform/MPC5748G/make/gcc/arch/perf.h + 1 + C:/NXP/S32DS_Power_v2017.R1/S32DS/S32_SDK_MPC574xx_RTM_1.0.0/middleware/tcpip/tcpip_stack/ports/platform/MPC5748G/make/gcc/arch/perf.h + + + + + S32_SDK_PATH + file:/C:/eclipse_home../S32DS/S32_SDK_MPC574xx_RTM_1.0.0 + + + diff --git a/flexray_adapter/flexray_adapter/.settings/com.freescale.s32ds.cross.wizard.prefs b/flexray_adapter/flexray_adapter/.settings/com.freescale.s32ds.cross.wizard.prefs new file mode 100644 index 00000000000000..c85bd487711c51 --- /dev/null +++ b/flexray_adapter/flexray_adapter/.settings/com.freescale.s32ds.cross.wizard.prefs @@ -0,0 +1,17 @@ +core=MPC5748G_Z4_0 +coreType=MPC5748G_Z4 +eclipse.preferences.version=1 +flashSize=1d0000 +flashStart=1000000 +fpu=None +groupName= +io= +language=c +library=ewl_c9x +pinSet= +processor=MPC5748G +productVersion=v1.2 b161201 +ramSize=40000 +ramStart=40000000 +toolchainVersion= +wizardVersion=1.0.0.201612011055 diff --git a/flexray_adapter/flexray_adapter/.settings/com.processorexpert.core.ide.newprojectwizard.prefs b/flexray_adapter/flexray_adapter/.settings/com.processorexpert.core.ide.newprojectwizard.prefs new file mode 100644 index 00000000000000..87ca305fb0deed --- /dev/null +++ b/flexray_adapter/flexray_adapter/.settings/com.processorexpert.core.ide.newprojectwizard.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +versionGenerated/versionGenerated=1.8.4.RT7_b1743-0713 diff --git a/flexray_adapter/flexray_adapter/.settings/language.settings.xml b/flexray_adapter/flexray_adapter/.settings/language.settings.xml new file mode 100644 index 00000000000000..9a4643a271f452 --- /dev/null +++ b/flexray_adapter/flexray_adapter/.settings/language.settings.xml @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/flexray_adapter/flexray_adapter/Debug_Configurations/flexray_adapter_debug_flash_pemicro.launch b/flexray_adapter/flexray_adapter/Debug_Configurations/flexray_adapter_debug_flash_pemicro.launch new file mode 100644 index 00000000000000..26816ba957be50 --- /dev/null +++ b/flexray_adapter/flexray_adapter/Debug_Configurations/flexray_adapter_debug_flash_pemicro.launch @@ -0,0 +1,174 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/flexray_adapter/flexray_adapter/Debug_Configurations/flexray_adapter_debug_ram_pemicro.launch b/flexray_adapter/flexray_adapter/Debug_Configurations/flexray_adapter_debug_ram_pemicro.launch new file mode 100644 index 00000000000000..07aa7c61e0b5dd --- /dev/null +++ b/flexray_adapter/flexray_adapter/Debug_Configurations/flexray_adapter_debug_ram_pemicro.launch @@ -0,0 +1,174 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/flexray_adapter/flexray_adapter/Debug_Configurations/flexray_adapter_debug_ram_pemicro_2.launch b/flexray_adapter/flexray_adapter/Debug_Configurations/flexray_adapter_debug_ram_pemicro_2.launch new file mode 100644 index 00000000000000..c4c3850b07dc70 --- /dev/null +++ b/flexray_adapter/flexray_adapter/Debug_Configurations/flexray_adapter_debug_ram_pemicro_2.launch @@ -0,0 +1,174 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/flexray_adapter/flexray_adapter/Documentation/flexray_adapter.txt b/flexray_adapter/flexray_adapter/Documentation/flexray_adapter.txt new file mode 100644 index 00000000000000..6ecc7a188f2143 --- /dev/null +++ b/flexray_adapter/flexray_adapter/Documentation/flexray_adapter.txt @@ -0,0 +1,350 @@ +============================================================================= +List of generated methods in project: flexray_adapter + +This text description is generated by Processor Expert. Do not modify it. +============================================================================= + +Module "intMan1" (component interrupt_manager) + - intMan1_INT_SYS_InstallHandler -Installs an interrupt handler routine for a given IRQ number. + - intMan1_INT_SYS_EnableIRQ -Enables an interrupt for a given IRQ number. + - intMan1_INT_SYS_DisableIRQ -Disables an interrupt for a given IRQ number. + - intMan1_INT_SYS_EnableIRQGlobal -Enables system interrupt. + - intMan1_INT_SYS_DisableIRQGlobal -Disable system interrupt. + - intMan1_INT_SYS_SetPriority -Set Interrupt Priority. + - intMan1_INT_SYS_GetPriority -Get Interrupt Priority. + - intMan1_INT_SYS_SetSoftwareIRQRequest -Set software interrupt request. + - intMan1_INT_SYS_ClearSoftwareIRQRequest -Clear software interrupt request. + - intMan1_INT_SYS_EnableIRQ_MC -Enables an interrupt for a given IRQ number, on the given cores. + - intMan1_INT_SYS_GetCoresForIRQ -Gets the cores on which an interrupt for the specified IRQ number is enabled. + - intMan1_INT_SYS_DisableIRQ_MC -Disables an interrupt for a given IRQ number, on the given cores. + - intMan1_INT_SYS_DisableIRQ_MC_All -Disables an interrupt for a given IRQ number, on all cores. + +Module "osif1" (component osif) + - osif1_OSIF_TimeDelay -Delays execution for a number of milliseconds. + - osif1_OSIF_MutexLock -Waits for a mutex and locks it. + - osif1_OSIF_MutexUnlock -Unlocks a previously locked mutex. + - osif1_OSIF_MutexCreate -Create an unlocked mutex. + - osif1_OSIF_MutexDestroy -Destroys a previously created mutex. + - osif1_OSIF_SemaWait -Decrement a semaphore with timeout. + - osif1_OSIF_SemaPost -Increment a semaphore. + - osif1_OSIF_SemaCreate -Creates a semaphore with a given value. + - osif1_OSIF_SemaDestroy -Destroys a previously created semaphore. + - osif1_OSIF_GetMilliseconds -Returns the number of miliseconds elapsed since starting the internal timer or starting the + scheduler. + +Module "FreeRTOS" (component FreeRTOS) + - FreeRTOS_xCoRoutineCreate -Create a new co-routine and add it to the list of co-routines that are ready to run. + - FreeRTOS_crDELAY -Delay a co-routine for a fixed period of time. crDELAY can only be called from the co-routine function + itself - not from within a function called by the co-routine function. This is because co-routines do not + maintain their own stack. + - FreeRTOS_crQUEUE_SEND -crQUEUE_SEND is a macro. The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + - FreeRTOS_crQUEUE_RECEIVE -crQUEUE_RECEIVE is a macro. The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + - FreeRTOS_crQUEUE_SEND_FROM_ISR -crQUEUE_SEND_FROM_ISR() is a macro. The macro's crQUEUE_SEND_FROM_ISR() and + crQUEUE_RECEIVE_FROM_ISR() are the co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + functions used by tasks. + - FreeRTOS_crQUEUE_RECEIVE_FROM_ISR -crQUEUE_SEND_FROM_ISR() is a macro. The macro's crQUEUE_SEND_FROM_ISR() and + crQUEUE_RECEIVE_FROM_ISR() are the co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + functions used by tasks. + - FreeRTOS_vCoRoutineSchedule -vCoRoutineSchedule() executes the highest priority co-routine that is able to run. The + co-routine will execute until it either blocks, yields or is preempted by a task. Co-routines execute + cooperatively so one co-routine cannot be preempted by another, but can be preempted by a task. + - FreeRTOS_xEventGroupCreate -Create a new RTOS event group. This function cannot be called from an interrupt. Event groups + are stored in variables of type EventGroupHandle_t. The number of bits (or flags) implemented within an event + group is 8 if configUSE_16_BIT_TICKS is set to 1, or 24 if configUSE_16_BIT_TICKS is set to 0. The dependency + on configUSE_16_BIT_TICKS results from the data type used for thread local storage in the internal + implementation of RTOS tasks. + - FreeRTOS_xEventGroupClearBits -Clear bits (flags) within an RTOS event group. This function cannot be called from an + interrupt. See xEventGroupClearBitsFromISR() for a version that can be called from an interrupt. + - FreeRTOS_xEventGroupClearBitsFromISR -A version of xEventGroupClearBits() that can be called from an interrupt. + - FreeRTOS_vEventGroupDelete -Delete an event group that was previously created using a call to xEventGroupCreate(). + - FreeRTOS_xEventGroupGetBits -Returns the current value of the bits in an event group. This function cannot be used from + an interrupt. + - FreeRTOS_xEventGroupGetBitsFromISR -A version of xEventGroupGetBits() that can be called from an ISR. + - FreeRTOS_xEventGroupSetBits -Set bits within an event group. This function cannot be called from an interrupt. + xEventGroupSetBitsFromISR() is a version that can be called from an interrupt. + - FreeRTOS_xEventGroupSetBitsFromISR -A version of xEventGroupSetBits() that can be called from an interrupt. Setting bits + in an event group is not a deterministic operation because there are an unknown number of tasks that may be + waiting for the bit or bits being set. FreeRTOS does not allow nondeterministic operations to be performed in + interrupts or from critical sections. Therefore xEventGroupSetBitFromISR() sends a message to the timer task + to have the set operation performed in the context of the timer task - where a scheduler lock is used in place + of a critical section. + - FreeRTOS_xEventGroupSync -Atomically set bits within an event group, then wait for a combination of bits to be set within + the same event group. This functionality is typically used to synchronise multiple tasks, where each task has + to wait for the other tasks to reach a synchronisation point before proceeding. This function cannot be used + from an interrupt. + - FreeRTOS_xEventGroupWaitBits -Read bits within an RTOS event group, optionally entering the Blocked state (with a timeout) + to wait for a bit or group of bits to become set. This function cannot be called from an interrupt. + - FreeRTOS_vQueueAddToRegistry -Assigns a name to a queue and adds the queue to the registry. + - FreeRTOS_xQueueAddToSet -Adds an RTOS queue or semaphore to a queue set that was previously created by a call to + xQueueCreateSet(). A receive (in the case of a queue) or take (in the case of a semaphore) operation must not + be performed on a member of a queue set unless a call to xQueueSelectFromSet() has first returned a handle to + that set member. + - FreeRTOS_xQueueCreate -Creates a new queue instance. This allocates the storage required by the new queue and returns a + handle for the queue. + - FreeRTOS_xQueueCreateSet -Queue sets provide a mechanism to allow an RTOS task to block (pend) on a read operation from + multiple RTOS queues or semaphores simultaneously. Note that there are simpler alternatives to using queue sets. + See the Blocking on Multiple Objects page for more information. + - FreeRTOS_vQueueDelete -Delete a queue - freeing all the memory allocated for storing of items placed on the queue. + - FreeRTOS_xQueueIsQueueEmptyFromISR -Queries a queue to determine if the queue is empty. This function should only be used + in an ISR. + - FreeRTOS_xQueueIsQueueFullFromISR -Queries a queue to determine if the queue is full. This function should only be used in + an ISR. + - FreeRTOS_uxQueueMessagesWaiting -A version of uxQueueMessagesWaiting() that can be called from an ISR. Return the number + of messages stored in a queue. + - FreeRTOS_uxQueueMessagesWaitingFromISR -This is a macro that calls the xQueueGenericSend() function. A version of + xQueueSendToBack() that will write to the queue even if the queue is full, overwriting data that is already + held in the queue. + - FreeRTOS_xQueueOverwriteFromISR -This is a macro that calls the xQueueGenericSendFromISR() function. A version of + xQueueOverwrite() that can be used in an ISR. xQueueOverwriteFromISR() is similar to xQueueSendToBackFromISR(), + but will write to the queue even if the queue is full, overwriting data that is already held in the queue. + - FreeRTOS_xQueuePeek -This is a macro that calls the xQueueGenericReceive() function. Receive an item from a queue without + removing the item from the queue. The item is received by copy so a buffer of adequate size must be provided. + The number of bytes copied into the buffer was defined when the queue was created. + - FreeRTOS_xQueuePeekFromISR -A version of xQueuePeek() that can be used from an interrupt service routine (ISR). Receive an + item from a queue without removing the item from the queue. The item is received by copy so a buffer of + adequate size must be provided. The number of bytes copied into the buffer was defined when the queue was + created. + - FreeRTOS_xQueueReceive -This is a macro that calls the xQueueGenericReceive() function. Receive an item from a queue. The + item is received by copy so a buffer of adequate size must be provided. The number of bytes copied into the + buffer was defined when the queue was created. + - FreeRTOS_xQueueReceiveFromISR -Receive an item from a queue. It is safe to use this function from within an interrupt + service routine. + - FreeRTOS_xQueueRemoveFromSet -Remove an RTOS queue or semaphore from a queue set. An RTOS queue or semaphore can only be + removed from a queue set if the queue or semaphore is empty. + - FreeRTOS_xQueueReset -Resets a queue to its original empty state. + - FreeRTOS_xQueueSelectFromSet -xQueueSelectFromSet() selects from the members of a queue set a queue or semaphore that + either contains data (in the case of a queue) or is available to take (in the case of a semaphore). + xQueueSelectFromSet() effectively allows a task to block (pend) on a read operation on all the queues and + semaphores in a queue set simultaneously. + - FreeRTOS_xQueueSelectFromSetFromISR -A version of xQueueSelectFromSet() that can be used from an interrupt service routine + (ISR). + - FreeRTOS_xQueueSend -This is a macro that calls xQueueGenericSend(). It is included for backward compatibility with + versions of FreeRTOS that did not include the xQueueSendToFront() and xQueueSendToBack() macros. It is + equivalent to xQueueSendToBack(). + - FreeRTOS_xQueueSendToFront -This is a macro that calls xQueueGenericSend(). Post an item to the front of a queue. The item + is queued by copy, not by reference. This function must not be called from an interrupt service routine. See + xQueueSendToFrontFromISR () for an alternative which may be used in an ISR. + - FreeRTOS_xQueueSendToBack -This is a macro that calls xQueueGenericSend(). It is equivalent to xQueueSend(). Post an item + to the back of a queue. The item is queued by copy, not by reference. This function must not be called from an + interrupt service routine. See xQueueSendToBackFromISR () for an alternative which may be used in an ISR. + - FreeRTOS_xQueueSendFromISR -This is a macro that calls xQueueGenericSendFromISR(). It is included for backward + compatibility with versions of FreeRTOS that did not include the xQueueSendToBackFromISR() and + xQueueSendToFrontFromISR() macros. Post an item into the back of a queue. It is safe to use this function from + within an interrupt service routine. + - FreeRTOS_xQueueSendToBackFromISR -This is a macro that calls xQueueGenericSendFromISR(). Post an item to the back of a + queue. It is safe to use this function from within an interrupt service routine. + - FreeRTOS_xQueueSendToFrontFromISR -This is a macro that calls xQueueGenericSendFromISR(). Post an item to the front of a + queue. It is safe to use this function from within an interrupt service routine. + - FreeRTOS_uxQueueSpacesAvailable -Return the number of free spaces in a queue. + - FreeRTOS_vSemaphoreCreateBinary -Macro that creates a semaphore by using the existing queue mechanism. The queue length is + 1 as this is a binary semaphore. The data size is 0 as we don't want to actually store any data - we just want + to know if the queue is empty or full. + - FreeRTOS_xSemaphoreCreateBinary -Function that creates a binary semaphore. Binary semaphores are either available, or not + available, hence binary. The semaphore is created in the 'empty' state, meaning the semaphore must first be + given before it can be taken (obtained) using the xSemaphoreTake() function. + - FreeRTOS_xSemaphoreCreateCounting -Macro that creates a counting semaphore by using the existing queue mechanism. Counting + semaphores are typically used for two things: 1. Counting events. 2. Resource management. + - FreeRTOS_xSemaphoreCreateMutex -Macro that creates a mutex semaphore by using the existing queue mechanism. Mutexes + created using this macro can be accessed using the xSemaphoreTake() and xSemaphoreGive() macros. The + xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros should not be used. + - FreeRTOS_xSemaphoreCreateRecursiveMutex -Macro that implements a recursive mutex by using the existing queue mechanism. + Mutexes created using this macro can be accessed using the xSemaphoreTakeRecursive() and + xSemaphoreGiveRecursive() macros. The xSemaphoreTake() and xSemaphoreGive() macros should not be used. + - FreeRTOS_vSemaphoreDelete -Deletes a semaphore, including mutex type semaphores and recursive semaphores. Do not delete a + semaphore that has tasks blocked on it (tasks that are in the Blocked state waiting for the semaphore to become + available). + - FreeRTOS_xSemaphoreGetMutexHolder -Return the handle of the task that holds the mutex specified by the function parameter, + if any. + - FreeRTOS_xSemaphoreGive -Macro to release a semaphore. The semaphore must have previously been created with a call to + xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or xSemaphoreCreateCounting(), and obtained using + sSemaphoreTake(). + - FreeRTOS_xSemaphoreGiveFromISR -Macro to release a semaphore. The semaphore must have previously been created with a call + to xSemaphoreCreateBinary() or xSemaphoreCreateCounting(). + - FreeRTOS_xSemaphoreGiveRecursive -Macro to recursively release, or 'give', a mutex type semaphore. The mutex must have + previously been created using a call to xSemaphoreCreateRecursiveMutex(); + - FreeRTOS_xSemaphoreTake -Macro to obtain a semaphore. The semaphore must have previously been created with a call to + xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or xSemaphoreCreateCounting(). + - FreeRTOS_xSemaphoreTakeFromISR -A version of xSemaphoreTake() that can be called from an ISR. Unlike xSemaphoreTake(), + xSemaphoreTakeFromISR() does not permit a block time to be specified. + - FreeRTOS_xSemaphoreTakeRecursive -Macro to recursively obtain, or 'take', a mutex type semaphore. The mutex must have + previously been created using a call to xSemaphoreCreateRecursiveMutex(); configUSE_RECURSIVE_MUTEXES must + be set to 1 in FreeRTOSConfig.h for this macro to be available. This macro must not be used on mutexes + created using xSemaphoreCreateMutex(). + - FreeRTOS_portSWITCH_TO_USER_MODE -Sets the calling task into User mode. Once in User mode a task cannot return to + Privileged mode. + - FreeRTOS_vTaskAllocateMPURegions -Memory regions are assigned to a restricted task when the task is created using a call + to xTaskCreateRestricted(). The regions can then be modified or redefined at run time using + vTaskAllocateMPURegions(). + - FreeRTOS_xTaskCreate -Create a new task and add it to the list of tasks that are ready to run. If you are using + FreeRTOS-MPU then it is recommended to use xTaskCreateRestricted() in place of xTaskCreate(). Using + xTaskCreate() with FreeRTOS-MPU allows tasks to be created to run in either Privileged or User modes (see the + description of uxPriority below). When Privileged mode it used the task will have access to the entire memory + map, when User mode is used the task will have access to only its stack. In both cases the MPU will not + automatically catch stack overflows, although the standard FreeRTOS stack overflow detection schemes can still + be used. xTaskCreateRestricted() permits much greater flexibility. + - FreeRTOS_xTaskCreateRestricted -Create a new Memory Protection Unit (MPU) restricted task and add it to the list of tasks + that are ready to run. + - FreeRTOS_vTaskDelay -Delay a task for a given number of ticks. The actual time that the task remains blocked depends on + the tick rate. The constant portTICK_PERIOD_MS can be used to calculate real time from the tick rate - with the + resolution of one tick period. + - FreeRTOS_vTaskDelete -Remove a task from the RTOS kernels management. The task being deleted will be removed from all + ready, blocked, suspended and event lists. + - FreeRTOS_taskDISABLE_INTERRUPTS -Macro to disable all maskable interrupts. + - FreeRTOS_taskENABLE_INTERRUPTS -Macro to enable microcontroller interrupts. + - FreeRTOS_taskENTER_CRITICAL -Macro to mark the start of a critical code region. Preemptive context switches cannot occur + when in a critical region. + - FreeRTOS_taskEXIT_CRITICAL -Macro to mark the end of a critical code region. Preemptive context switches cannot occur when + in a critical region. + - FreeRTOS_xTaskGetApplicationTaskTag -Returns the ¡®tag?? value associated with a task. The meaning and use of the tag value + is defined by the application writer. The RTOS kernel itself will not normally access the tag value. + - FreeRTOS_xTaskGetCurrentTaskHandle -Returns the handle of the currently running (calling) task. + - FreeRTOS_uxTaskGetNumberOfTasks -Return the number of tasks that the RTOS kernel is currently managing. + - FreeRTOS_vTaskGetRunTimeStats -Return information on the amount of processing time that has been used by each task. This + function can then be used to present this information in a tabular format. + - FreeRTOS_uxTaskGetStackHighWaterMark -Returns the high water mark of the stack associated with xTask. That is, the + minimum free stack space there has been (in words, so on a 32 bit machine a value of 1 means 4 bytes) since the + task started. The smaller the returned number the closer the task has come to overflowing its stack. + - FreeRTOS_uxTaskGetSystemState -Populates an TaskStatus_t structure for each task in the system. TaskStatus_t structures + contain, among other things, members for the task handle, task name, task priority, task state, and total + amount of run time consumed by the task. See the TaskStatus_t structure definition in this file for the full + member list. + - FreeRTOS_xTaskGetTickCount -This function cannot be called from an ISR. Use xTaskGetTickCountFromISR() instead. + - FreeRTOS_xTaskGetTickCountFromISR -A version of xTaskGetTickCount() that can be called from an ISR. + - FreeRTOS_vTaskList -vTaskList() is a utility function provided for convenience only. It is not considered part of the + kernel. + - FreeRTOS_vTaskResume -Resumes a suspended task. A task that has been suspended by one or more calls to vTaskSuspend () + will be made available for running again by a single call to vTaskResume (). + - FreeRTOS_xTaskResumeAll -Resumes the scheduler after it was suspended using a call to vTaskSuspendAll(). xTaskResumeAll() + only resumes the scheduler. It does not unsuspend tasks that were previously suspended by a call to + vTaskSuspend(). + - FreeRTOS_xTaskResumeFromISR -A function to resume a suspended task that can be called from within an ISR. A task that has + been suspended by one of more calls to vTaskSuspend() will be made available for running again by a single call + to xTaskResumeFromISR(). + - FreeRTOS_vTaskStepTick -If the RTOS is configured to use tickless idle functionality then the tick interrupt will be + stopped, and the microcontroller placed into a low power state, whenever the Idle task is the only task able to + execute. Upon exiting the low power state the tick count value must be corrected to account for the time that + passed while it was stopped. + - FreeRTOS_vTaskSuspendAll -Suspends the scheduler without disabling interrupts. Context switches will not occur while the + scheduler is suspended. RTOS ticks that occur while the scheduler is suspended will be held pending until the + scheduler has been unsuspended using a call to xTaskResumeAll(). + - FreeRTOS_taskYIELD -Macro for forcing a context switch. + - FreeRTOS_vTaskStartScheduler -Starts the RTOS scheduler. After calling the RTOS kernel has control over which tasks are + executed and when. The idle task and optionally the timer daemon task are created automatically when the RTOS + scheduler is started. + - FreeRTOS_vTaskEndScheduler -Stops the RTOS kernel tick. All created tasks will be automatically deleted and multitasking + (either preemptive or cooperative) will stop. Execution then resumes from the point where vTaskStartScheduler() + was called, as if vTaskStartScheduler() had just returned. + - FreeRTOS_xTaskCallApplicationTaskHook -Calls the hook function associated with xTask. Passing xTask as NULL has the effect + of calling the Running tasks (the calling task) hook function. + +Module "pin_mux" (component PinSettings) + - pin_mux_PINS_DRV_Init -This function configures the pins with the options provided in the provided structure + - pin_mux_PINS_DRV_SetPullSel -This function configures the internal resistor + - pin_mux_PINS_DRV_SetOutputBuffer -This function configures the output buffer + - pin_mux_PINS_DRV_SetInputBuffer -This function configures the input buffer + - pin_mux_PINS_DRV_ConfigIntFilterClock -This function configures the interrupt filter clock prescaler + - pin_mux_PINS_DRV_SetExInt -This function configures the external interrupt + - pin_mux_PINS_DRV_ClearPinExIntFlag -This function clears the individual pin external interrupt status flag + - pin_mux_PINS_DRV_GetPinExIntFlag -This function gets the individual pin external interrupt status flag + - pin_mux_PINS_DRV_ClearExIntFlag -This function clears the entire external interrupt status flag + - pin_mux_PINS_DRV_GetExIntFlag -This function gets the individual pin external interrupt status flag + - pin_mux_PINS_DRV_WritePin -This function writes the given pin from a port, with the given value ('0' represents LOW, '1' + represents HIGH) + - pin_mux_PINS_DRV_WritePins -This function writes all pins configured as output with the values given in the parameter pins. + '0' represents LOW, '1' represents HIGH + - pin_mux_PINS_DRV_GetPinsOutput -This function returns the current output that is written to a port. Only pins that are + configured as output will have meaningful values + - pin_mux_PINS_DRV_SetPins -This function configures output pins listed in parameter pins (bits that are '1') to have a + value of 'set' (HIGH). Pins corresponding to '0' will be unaffected + - pin_mux_PINS_DRV_ClearPins -This function configures output pins listed in parameter pins (bits that are '1') to have a + 'cleared' value (LOW). Pins corresponding to '0' will be unaffected + - pin_mux_PINS_DRV_TogglePins -This function toggles output pins listed in parameter pins (bits that are '1'). Pins + corresponding to '0' will be unaffected + - pin_mux_PINS_DRV_ReadPins -This function returns the current input values from a port. Only pins configured as input will + have meaningful values + +Module "clockMan1" (component clock_manager) + - clockMan1_CLOCK_SYS_Init -Install pre-defined clock configurations. + - clockMan1_CLOCK_SYS_UpdateConfiguration -Set system clock configuration according to pre-defined structure. + - clockMan1_CLOCK_SYS_SetConfiguration -Set system clock configuration. + - clockMan1_CLOCK_SYS_GetCurrentConfiguration -Get current system clock configuration. + - clockMan1_CLOCK_SYS_GetErrorCallback -Get the callback which returns error in last clock switch. + - clockMan1_CLOCK_SYS_GetFreq -Gets the clock frequency for a specific clock name. + +Module "tcpip_middleware" (component tcpip) + +Module "linflexd_uart1" (component linflexd_uart) + - linflexd_uart1_LINFLEXD_UART_DRV_SetBaudRate -Sets the baudrate for UART communication. + - linflexd_uart1_LINFLEXD_UART_DRV_GetBaudRate -Retrieves the baudrate of UART communication. + - linflexd_uart1_LINFLEXD_UART_DRV_Init -Initializes an UART operation instance. + - linflexd_uart1_LINFLEXD_UART_DRV_Deinit -Shuts down the UART by disabling interrupts and transmitter/receiver. + - linflexd_uart1_LINFLEXD_UART_DRV_InstallRxCallback -Installs callback function for the UART receive. + - linflexd_uart1_LINFLEXD_UART_DRV_InstallTxCallback -Installs callback function for the UART transmit. + - linflexd_uart1_LINFLEXD_UART_DRV_InstallErrorCallback -Installs callback function for the UART error cases. + - linflexd_uart1_LINFLEXD_UART_DRV_SendDataBlocking -Sends data out through the UART module using a blocking method. + - linflexd_uart1_LINFLEXD_UART_DRV_SendData -Sends data out through the UART module using a non-blocking method. This + enables an a-sync method for transmitting data. When used with a non-blocking receive, the UART can perform a + full duplex operation. Non-blocking means that the function returns immediately. The application has to get the + transmit status to know when the transmit is complete. + - linflexd_uart1_LINFLEXD_UART_DRV_GetTransmitStatus -Returns whether the previous transmit is complete. + - linflexd_uart1_LINFLEXD_UART_DRV_AbortSendingData -Terminates a non-blocking transmission early. + - linflexd_uart1_LINFLEXD_UART_DRV_ReceiveDataBlocking -Gets data from the UART module by using a blocking method. Blocking + means that the function does not return until the receive is complete. + - linflexd_uart1_LINFLEXD_UART_DRV_ReceiveData -Gets data from the UART module by using a non-blocking method. This enables + an a-sync method for receiving data. When used with a non-blocking transmission, the UART can perform a full + duplex operation. Non-blocking means that the function returns immediately. The application has to get the + receive status to know when the receive is complete. + - linflexd_uart1_LINFLEXD_UART_DRV_GetReceiveStatus -Returns whether the previous receive is complete. + - linflexd_uart1_LINFLEXD_UART_DRV_AbortReceivingData -Terminates a non-blocking receive early. + - linflexd_uart1_LINFLEXD_UART_DRV_SetTxBuffer -Updates the internal reference to the tx buffer. + - linflexd_uart1_LINFLEXD_UART_DRV_SetRxBuffer -Updates the internal reference to rx buffer. + +Module "dmaController1" (component edma) + - dmaController1_EDMA_DRV_Init -Initializes the eDMA module. + - dmaController1_EDMA_DRV_Deinit -Shuts down the eDMA module. + - dmaController1_EDMA_DRV_ChannelInit -Initializes a eDMA virtualChannel. + - dmaController1_EDMA_DRV_ReleaseChannel -Releases an eDMA virtualChannel. + - dmaController1_EDMA_DRV_StartChannel -Starts an eDMA virtualChannel. + - dmaController1_EDMA_DRV_StopChannel -Stops the eDMA virtualChannel. + - dmaController1_EDMA_DRV_InstallCallback -Registers the callback function and the parameter for eDMA virtualChannel. + - dmaController1_EDMA_DRV_GetChannelStatus -Gets the eDMA virtualChannel status. + - dmaController1_EDMA_DRV_PushConfigToReg -Copies the virtualChannel configuration to the TCD registers. + - dmaController1_EDMA_DRV_PushConfigToSTCD -Copies the virtualChannel configuration to the software TCD structure. + - dmaController1_EDMA_DRV_ConfigSingleBlockTransfer -Configures a simple single block data transfer with DMA. This function + configures the descriptor for a single block transfer. + - dmaController1_EDMA_DRV_ConfigLoopTransfer -Configures the DMA transfer in loop mode. + - dmaController1_EDMA_DRV_ConfigScatterGatherTransfer -Configures the DMA transfer in a scatter-gather mode. + - dmaController1_EDMA_DRV_ConfigMultiBlockTransfer -Configures a multiple block data transfer with DMA. This function + configures the descriptor for a multi block transfer. + - dmaController1_EDMA_DRV_CancelTransfer -Cancels the remaining data transfer. + - dmaController1_EDMA_DRV_SetChannelRequest -Configures the DMA request for the eDMA virtualChannel. + - dmaController1_EDMA_DRV_ClearTCD -Clears all registers to 0 for the virtualChannel's TCD. + - dmaController1_EDMA_DRV_SetSrcAddr -Configures the source address for the eDMA virtualChannel. + - dmaController1_EDMA_DRV_SetSrcOffset -Configures the source address signed offset for the eDMA virtualChannel. + - dmaController1_EDMA_DRV_SetSrcReadChunkSize -Configures the source data chunk size (transferred in a read sequence). + - dmaController1_EDMA_DRV_SetDestAddr -Configures the destination address for the eDMA virtualChannel. + - dmaController1_EDMA_DRV_SetDestOffset -Configures the destination address signed offset for the eDMA virtualChannel. + - dmaController1_EDMA_DRV_SetDestWriteChunkSize -Configures the destination data chunk size (transferred in a write sequence) + . + - dmaController1_EDMA_DRV_SetMinorLoopBlockSize -Configures the number of bytes to be transferred in each service request of + the virtualChannel. + - dmaController1_EDMA_DRV_SetMajorLoopIterationCount -Configures the number of major loop iterations. + - dmaController1_EDMA_DRV_GetRemainingMajorIterationsCount -Returns the remaining major loop iteration count. + - dmaController1_EDMA_DRV_SetScatterGatherLink -Configures the memory address of the next TCD, in scatter/gather mode. + - dmaController1_EDMA_DRV_DisableRequestsOnTransferComplete -Disables/Enables the DMA request after the major loop completes + for the TCD. + - dmaController1_EDMA_DRV_SetSrcLastAddrAdjustment -Configures the source address last adjustment. + - dmaController1_EDMA_DRV_SetDestLastAddrAdjustment -Configures the destination address last adjustment. + - dmaController1_EDMA_DRV_ConfigureInterrupt -Disables/Enables the virtualChannel interrupt requests. + - dmaController1_EDMA_DRV_TriggerSwRequest -Triggers a sw request for the current virtualChannel. + +Module "Cpu" (component MPC5748G_176) + - Cpu_SystemInit -This method configures the oscillator (PLL) that is part of the microcontroller device. SystemInit is + called from startup_device file. + - Cpu_SystemCoreClockUpdate -SystemCoreClockUpdate evaluates the clock register settings and calculates the current core + clock. + - Cpu_SystemSoftwareReset -This method initiates a software rest of the microcontroller. + +=================================================================================== diff --git a/flexray_adapter/flexray_adapter/Documentation/flexray_adapter_Settings.previous.xml b/flexray_adapter/flexray_adapter/Documentation/flexray_adapter_Settings.previous.xml new file mode 100644 index 00000000000000..dfcec7af9607e7 --- /dev/null +++ b/flexray_adapter/flexray_adapter/Documentation/flexray_adapter_Settings.previous.xml @@ -0,0 +1,117 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/flexray_adapter/flexray_adapter/Documentation/flexray_adapter_Settings.xml b/flexray_adapter/flexray_adapter/Documentation/flexray_adapter_Settings.xml new file mode 100644 index 00000000000000..784903839bf785 --- /dev/null +++ b/flexray_adapter/flexray_adapter/Documentation/flexray_adapter_Settings.xml @@ -0,0 +1,145 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/flexray_adapter/flexray_adapter/Generated_Code/Cpu.c b/flexray_adapter/flexray_adapter/Generated_Code/Cpu.c new file mode 100644 index 00000000000000..e1fdc45be6ca7f --- /dev/null +++ b/flexray_adapter/flexray_adapter/Generated_Code/Cpu.c @@ -0,0 +1,77 @@ +/** ################################################################### +** This component module is generated by Processor Expert. Do not modify it. +** Filename : Cpu.c +** Project : flexray_adapter +** Processor : MPC5748G_176 +** Component : MPC5748G_176 +** Version : Component 01.197, Driver 01.00, CPU db: 3.00.000 +** Datasheet : MPC5748G RM Rev. 6, 10/2017 +** Compiler : GNU C Compiler +** Date/Time : 2018-10-16, 17:47, # CodeGen: 0 +** Abstract : +** +** Settings : +** +** Contents : +** SystemInit - void SystemInit(void); +** SystemCoreClockUpdate - void SystemCoreClockUpdate(void); +** SystemSoftwareReset - void SystemSoftwareReset(void); +** +** (c) Freescale Semiconductor, Inc. +** 2004 All Rights Reserved +** +** Copyright 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All Rights Reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** ###################################################################*/ +/*! +** @file Cpu.c +** @version 01.00 +** @brief +** +*/ +/*! +** @addtogroup Cpu_module Cpu module documentation +** @{ +*/ + +/* MODULE Cpu. */ + +/* {Default RTOS Adapter} No RTOS includes */ +#include "Cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* TBD Cpu configuration will be generated here. */ + +#ifdef __cplusplus +} +#endif + +/* END Cpu. */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.1 [05.21] +** for the NXP C55 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/flexray_adapter/flexray_adapter/Generated_Code/Cpu.h b/flexray_adapter/flexray_adapter/Generated_Code/Cpu.h new file mode 100644 index 00000000000000..a55fd7b9d1c083 --- /dev/null +++ b/flexray_adapter/flexray_adapter/Generated_Code/Cpu.h @@ -0,0 +1,96 @@ +/* ################################################################### +** This component module is generated by Processor Expert. Do not modify it. +** Filename : Cpu.h +** Project : flexray_adapter +** Processor : MPC5748G_176 +** Component : MPC5748G_176 +** Version : Component 01.197, Driver 01.00, CPU db: 3.00.000 +** Datasheet : MPC5748G RM Rev. 6, 10/2017 +** Compiler : GNU C Compiler +** Date/Time : 2018-10-16, 17:49, # CodeGen: 1 +** Abstract : +** +** Settings : +** +** Contents : +** SystemInit - void SystemInit(void); +** SystemCoreClockUpdate - void SystemCoreClockUpdate(void); +** SystemSoftwareReset - void SystemSoftwareReset(void); +** +** (c) Freescale Semiconductor, Inc. +** 2004 All Rights Reserved +** +** Copyright 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All Rights Reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** ###################################################################*/ +/*! +** @file Cpu.h +** @version 01.00 +** @brief +** +*/ +/*! +** @addtogroup Cpu_module Cpu module documentation +** @{ +*/ + +#ifndef Cpu_H +#define Cpu_H + +/* MODULE Cpu. */ + +/*Include shared modules, which are used for whole project*/ +#include "device_registers.h" +#include "clock_manager.h" +#include "interrupt_manager.h" +#include "osif.h" +#include "enet_driver.h" +#include "linflexd_uart_driver.h" +#include "edma_driver.h" +#include "system_MPC5748G.h" + +/* Including needed modules to compile this module/procedure */ +#include "FreeRTOS.h" +#include "pin_mux.h" +#include "clockMan1.h" +#include "linflexd_uart1.h" +#include "dmaController1.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* Cpu configuration will be declared here. */ + +#ifdef __cplusplus +} +#endif + +/* END Cpu. */ + +#endif +/* Cpu_H */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.1 [05.21] +** for the NXP C55 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/flexray_adapter/flexray_adapter/Generated_Code/FreeRTOSConfig.h b/flexray_adapter/flexray_adapter/Generated_Code/FreeRTOSConfig.h new file mode 100644 index 00000000000000..c29fa7069cbdd1 --- /dev/null +++ b/flexray_adapter/flexray_adapter/Generated_Code/FreeRTOSConfig.h @@ -0,0 +1,190 @@ +/* + FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro defined. + * The macro is used for development validation. + * + * @section [global] + * Violates MISRA 2012 Required Rule 3.1, C comment contains C++ comment. + * Detections are URL links from FreeRTOS header text. + * + */ + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( 40000000UL ) +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configMAX_PRIORITIES ( 8 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 512 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 49152 ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_RECURSIVE_MUTEXES 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 0 + +/* API functions definitions */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xQueueGetMutexHolder 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* Additional settings can be defined in the property Settings > User settings > Definitions of the FreeRTOS component */ +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 2 +#if defined(__GNUC__) && !defined(__ASSEMBLER__) +#include "device_registers.h" +#include "devassert.h" +#endif + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Run time stats gathering definitions. */ +#ifdef __ICCARM__ + /* The #ifdef just prevents this C specific syntax from being included in + assembly files. */ + void vMainConfigureTimerForRunTimeStats( void ); + unsigned long ulMainGetRunTimeCounterValue( void ); +#endif +#if defined(__GNUC__) && !defined(__ASSEMBLER__) + /* The #ifdef just prevents this C specific syntax from being included in + assembly files. */ + void vMainConfigureTimerForRunTimeStats( void ); + unsigned long ulMainGetRunTimeCounterValue( void ); +#endif + + +#define configGENERATE_RUN_TIME_STATS 0 /* 1: generate runtime statistics; 0: no runtime statistics */ + +/* Calypso specific: pit channel to use 0-15 */ +#define configUSE_PIT_CHANNEL (15) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configMAX_API_CALL_INTERRUPT_PRIORITY (15) + +/* Definition assert() function. */ +#define configASSERT(x) DEV_ASSERT(x) + + +/* Tickless Idle Mode */ +#define configUSE_TICKLESS_IDLE 0 +#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 +#define configUSE_TICKLESS_IDLE_DECISION_HOOK 0 +#endif /* FREERTOS_CONFIG_H */ diff --git a/flexray_adapter/flexray_adapter/Generated_Code/clockMan1.c b/flexray_adapter/flexray_adapter/Generated_Code/clockMan1.c new file mode 100644 index 00000000000000..401eb024fd1609 --- /dev/null +++ b/flexray_adapter/flexray_adapter/Generated_Code/clockMan1.c @@ -0,0 +1,818 @@ +/* ################################################################### +** This component module is generated by Processor Expert. Do not modify it. +** Filename : clockMan1.c +** Project : flexray_adapter +** Processor : MPC5748G_176 +** Component : clock_manager +** Version : Component SDK_MPC574x_06, Driver 01.00, CPU db: 3.00.000 +** Repository : SDK_MPC574x_06 +** Compiler : GNU C Compiler +** Date/Time : 2018-10-16, 17:49, # CodeGen: 1 +** +** Copyright 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All Rights Reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** ###################################################################*/ +/*! +** @file clockMan1.c +** @version 01.00 +*/ +/*! +** @addtogroup clockMan1_module clockMan1 module documentation +** @{ +*/ + +/* clockMan1. */ + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.7, External variable could be made static. + * The external variables will be used in other source files, with the same initialized values. + */ + +#include "clockMan1.h" +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Required Rule 9.4, Duplicate initialization of object element. + * It's the only way to initialize an array that is member of struct. + * + */ +/* ************************************************************************* + * Configuration structure for peripheral clock configuration 0 + * ************************************************************************* */ +/*! @brief peripheral clock configuration 0 */ +mc_me_peripheral_clock_config_t peripheralClockMcMeConfig0[] = { + { + .clockName = ADC0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = ADC1_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = BCTU0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = CMP0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = CMP1_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = CMP2_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = CRC0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = DMA0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = DMAMUX0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = DSPI0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = DSPI1_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = DSPI2_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = DSPI3_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = ENET0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = FLEXCAN0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = FLEXCAN1_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = FLEXCAN2_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = FLEXCAN3_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = FLEXCAN4_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = FLEXCAN5_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = FLEXCAN6_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = FLEXCAN7_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = FLEXRAY0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = IIC0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = IIC1_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = IIC2_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = IIC3_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN1_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN2_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN3_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN4_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN5_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN6_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN7_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN8_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN9_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN10_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN11_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN12_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN13_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN14_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN15_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN16_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = LIN17_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = MEMU0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = MEMU1_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = MLB0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = PITRTI0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = RTC0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = SAI0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = SAI1_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = SAI2_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = SDHC0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = SPI0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = SPI1_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = SPI2_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = SPI3_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = SPI4_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = SPI5_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = SIUL0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = USBOTG0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = USBSPH0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = WKPU0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = eMIOS0_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = eMIOS1_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = eMIOS2_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = ENET1_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = ENET0_TIME_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_2, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, + { + .clockName = DMAMUX1_CLK, + .mc_me_RunPeriphConfig = MC_ME_PERIPH_CONFIG_1, + .mc_me_LowPowerPeriphConfig = MC_ME_PERIPH_CONFIG_1, + }, +}; + +/* ************************************************************************* + * Configuration structure for Clock Configuration 0 + * ************************************************************************* */ +/*! @brief User Configuration structure clock_managerCfg_0 */ +clock_manager_user_config_t clockMan1_InitConfig0 = { + + /*! @brief Configuration of MC_ME */ + .mcmeConfig = + { + .run0 = + { + .clocksEnabled = + { + .irc0 = false, + .irc1 = true, + .xosc0 = false, + .xosc1 = false, + .pll0 = false, + }, + .sysclk = CGM_SYSTEM_CLOCK_SRC_FIRC, + }, + + .run1 = + { + .clocksEnabled = + { + .irc0 = false, + .irc1 = true, + .xosc0 = false, + .xosc1 = false, + .pll0 = false, + }, + .sysclk = CGM_SYSTEM_CLOCK_SRC_FIRC, + }, + + .run2 = + { + .clocksEnabled = + { + .irc0 = false, + .irc1 = true, + .xosc0 = false, + .xosc1 = false, + .pll0 = false, + }, + .sysclk = CGM_SYSTEM_CLOCK_SRC_FIRC, + }, + + .run3 = + { + .clocksEnabled = + { + .irc0 = false, + .irc1 = true, + .xosc0 = false, + .xosc1 = false, + .pll0 = false, + }, + .sysclk = CGM_SYSTEM_CLOCK_SRC_FIRC, + }, + + .drun = + { + .clocksEnabled = + { + .irc0 = true, + .irc1 = true, + .xosc0 = true, + .xosc1 = true, + .pll0 = true, + }, + .sysclk = CGM_SYSTEM_CLOCK_SRC_PLL_PHI0, + }, + + .stop0 = + { + .clocksEnabled = + { + .irc0 = false, + .irc1 = true, + .xosc0 = false, + .xosc1 = false, + .pll0 = false, + }, + .sysclk = CGM_SYSTEM_CLOCK_SRC_FIRC, + }, + + .standby0 = + { + .clocksEnabled = + { + .irc0 = false, + .irc1 = true, + .xosc0 = false, + .xosc1 = false, + .pll0 = false, + }, + .sysclk = CGM_SYSTEM_CLOCK_SRC_FIRC, + }, + + .safe = + { + .clocksEnabled = + { + .irc0 = false, + .irc1 = true, + .xosc0 = false, + .xosc1 = false, + .pll0 = false, + }, + .sysclk = CGM_SYSTEM_CLOCK_SRC_FIRC, + }, + + .reset = + { + .clocksEnabled = + { + .irc0 = false, + .irc1 = true, + .xosc0 = false, + .xosc1 = false, + .pll0 = false, + }, + .sysclk = CGM_SYSTEM_CLOCK_SRC_FIRC, + }, + + + + .lpurun = + { + .clocksEnabled = + { + .irc0 = false, + .irc1 = true, + .xosc0 = false, + .xosc1 = false, + .pll0 = false, + }, + .sysclk = CGM_SYSTEM_CLOCK_SRC_FIRC, + }, + + .lpustop = + { + .clocksEnabled = + { + .irc0 = false, + .irc1 = true, + .xosc0 = false, + .xosc1 = false, + .pll0 = false, + }, + .sysclk = CGM_SYSTEM_CLOCK_SRC_FIRC, + }, + + .lpustandby = + { + .clocksEnabled = + { + .irc0 = false, + .irc1 = true, + .xosc0 = false, + .xosc1 = false, + .pll0 = false, + }, + .sysclk = CGM_SYSTEM_CLOCK_SRC_FIRC, + }, + + .periphRunConfig = + { + { + /* MC_ME_PERIPH_CONFIG_0 */ + .reset = false, + .safe = false, + .test = false, + .drun = false, + .run0 = false, + .run1 = false, + .run2 = false, + .run3 = false, + }, + { + /* MC_ME_PERIPH_CONFIG_1 */ + .reset = false, + .safe = true, + .test = false, + .drun = true, + .run0 = true, + .run1 = true, + .run2 = true, + .run3 = true, + }, + { + /* MC_ME_PERIPH_CONFIG_2 */ + .reset = false, + .safe = true, + .test = false, + .drun = false, + .run0 = true, + .run1 = true, + .run2 = true, + .run3 = true, + }, + { + /* MC_ME_PERIPH_CONFIG_3 */ + .reset = false, + .safe = false, + .test = false, + .drun = false, + .run0 = false, + .run1 = false, + .run2 = false, + .run3 = false, + }, + { + /* MC_ME_PERIPH_CONFIG_4 */ + .reset = false, + .safe = false, + .test = false, + .drun = false, + .run0 = false, + .run1 = false, + .run2 = false, + .run3 = false, + }, + { + /* MC_ME_PERIPH_CONFIG_5 */ + .reset = false, + .safe = false, + .test = false, + .drun = false, + .run0 = false, + .run1 = false, + .run2 = false, + .run3 = false, + }, + { + /* MC_ME_PERIPH_CONFIG_6 */ + .reset = false, + .safe = false, + .test = false, + .drun = false, + .run0 = false, + .run1 = false, + .run2 = false, + .run3 = false, + }, + { + /* MC_ME_PERIPH_CONFIG_7 */ + .reset = false, + .safe = false, + .test = false, + .drun = false, + .run0 = false, + .run1 = false, + .run2 = false, + .run3 = false, + }, + }, + .periphLowPowerConfig = + { + { + /* MC_ME_PERIPH_CONFIG_0 */ + .halt0 = false, + .standby0 = false, + .stop0 = false, + }, + { + /* MC_ME_PERIPH_CONFIG_1 */ + .halt0 = false, + .standby0 = true, + .stop0 = true, + }, + { + /* MC_ME_PERIPH_CONFIG_2 */ + .halt0 = false, + .standby0 = false, + .stop0 = false, + }, + { + /* MC_ME_PERIPH_CONFIG_3 */ + .halt0 = false, + .standby0 = false, + .stop0 = false, + }, + { + /* MC_ME_PERIPH_CONFIG_4 */ + .halt0 = false, + .standby0 = false, + .stop0 = false, + }, + { + /* MC_ME_PERIPH_CONFIG_5 */ + .halt0 = false, + .standby0 = false, + .stop0 = false, + }, + { + /* MC_ME_PERIPH_CONFIG_6 */ + .halt0 = false, + .standby0 = false, + .stop0 = false, + }, + { + /* MC_ME_PERIPH_CONFIG_7 */ + .halt0 = false, + .standby0 = false, + .stop0 = false, + }, + }, + .count = 70, + .peripherals = peripheralClockMcMeConfig0, + }, + + .cgmConfig = + { + .sc_dc0 = CGM_CLOCK_DIV_BY_1, + .sc_dc1 = CGM_CLOCK_DIV_BY_2, + .sc_dc2 = CGM_CLOCK_DIV_BY_4, + .sc_dc3 = CGM_CLOCK_DIV_BY_4, + .sc_dc4 = CGM_CLOCK_DIV_BY_2, + .sc_dc5 = CGM_CLOCK_DIV_BY_2, + .sc_dc6 = CGM_CLOCK_DIV_BY_8, + + .ac2_sc = CGM_ENETx_SOURCE_F40, + + .ac4_sc = CGM_USDHCx_SOURCE_F40, + + .ac5_sc = CGM_PLL_REFERENCE_FXOSC, + + .ac6_sc = CGM_CLOCKOUT0_SRC_FXOSC, + .ac6_dc0 = CGM_CLOCK_DIV_BY_1, + + .ac8_sc = CGM_SPI0_SOURCE_F40, + + .ac9_sc = CGM_FLEXCANx_SOURCE_FS80, + + .clkout1_sc = CGM_CLOCKOUT1_SRC_FXOSC_DIVIDED, + .clkout1_dc = CGM_CLOCK_DIV_BY_1, + + }, + + .cgmcsConfig = + { + .irc0Config = + { + .divider = IRC_CLOCK_DIV_BY_1, + }, + .irc1Config = + { + .divider = IRC_CLOCK_DIV_BY_1, + }, + .xosc0Config = + { + .freq = 32768, + .autoLevelControl = true, + .startupDelay = 1, + .divider = XOSC_CLOCK_DIV_BY_1, + }, + .xosc1Config = + { + .freq = 40000000, + .startupDelay = 1, + .divider = XOSC_CLOCK_DIV_BY_1, + .bypassOption = XOSC_USE_CRYSTAL, + .mode = XOSC_FULL_SWING_PIERCE_MODE, + }, + .pll0Config = + { + .predivider = PLLDIG_CLOCK_PREDIV_BY_2, + .denominatorFracLoopDiv = 9999, + .numeratorFracLoopDiv = 0, + .mulFactorDiv = 32, + .phi0Divider = PLLDIG_PHI_DIV_BY_4, + .phi1Divider = PLLDIG_PHI_DIV_BY_4, + .modulation = false, + .modulationPeriod = 0, + .incrementStep = 0, + .sigmaDelta = false, + .secondOrderSigmaDelta = false, + .thirdOrderSigmaDelta = false, + .ditherControl = false, + .ditherControlValue = 0, + }, + }, + +}; + +/*! @brief Array of pointers to User configuration structures */ +clock_manager_user_config_t const * g_clockManConfigsArr[] = { + &clockMan1_InitConfig0 +}; +/*! @brief Array of pointers to User defined Callbacks configuration structures */ +clock_manager_callback_user_config_t * g_clockManCallbacksArr[] = {(void*)0}; +/* END clockMan1. */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.1 [05.21] +** for the NXP C55 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/flexray_adapter/flexray_adapter/Generated_Code/clockMan1.h b/flexray_adapter/flexray_adapter/Generated_Code/clockMan1.h new file mode 100644 index 00000000000000..b7427f228f4780 --- /dev/null +++ b/flexray_adapter/flexray_adapter/Generated_Code/clockMan1.h @@ -0,0 +1,98 @@ +/* ################################################################### +** This component module is generated by Processor Expert. Do not modify it. +** Filename : clockMan1.h +** Project : flexray_adapter +** Processor : MPC5748G_176 +** Component : clock_manager +** Version : Component SDK_MPC574x_06, Driver 01.00, CPU db: 3.00.000 +** Repository : SDK_MPC574x_06 +** Compiler : GNU C Compiler +** Date/Time : 2018-10-16, 17:47, # CodeGen: 0 +** Contents : +** CLOCK_SYS_Init - status_t CLOCK_SYS_Init(clock_manager_user_config_t const **... +** CLOCK_SYS_UpdateConfiguration - status_t CLOCK_SYS_UpdateConfiguration(uint8_t... +** CLOCK_SYS_SetConfiguration - status_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const * config); +** CLOCK_SYS_GetCurrentConfiguration - uint8_t CLOCK_SYS_GetCurrentConfiguration(void); +** CLOCK_SYS_GetErrorCallback - clock_manager_callback_user_config_t* CLOCK_SYS_GetErrorCallback(void); +** CLOCK_SYS_GetFreq - status_t CLOCK_SYS_GetFreq(clock_names_t clockName,uint32_t * frequency); +** +** Copyright 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All Rights Reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** ###################################################################*/ +/*! +** @file clockMan1.h +** @version 01.00 +*/ +/*! +** @addtogroup clockMan1_module clockMan1 module documentation +** @{ +*/ +#ifndef clockMan1_H +#define clockMan1_H +/* MODULE clockMan1. */ + +#include +#include + +/* Include inherited beans */ +#include "Cpu.h" + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. + * Application or driver example may not use all symbols that are + * generated by configurations generator. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.11, When an array with external linkage + * is declared, its size should be explicitly specified. + * The number of configurations/callbacks can be zero. + * On the other side C language forbids declaring array of size zero. + */ +/*! @brief User configuration structure 0 */ +extern mc_me_peripheral_clock_config_t peripheralClockMcMeConfig0[]; +extern clock_manager_user_config_t clockMan1_InitConfig0; + +/*! @brief Count of user configuration structures */ +#define CLOCK_MANAGER_CONFIG_CNT 1U + +/*! @brief Array of pointers to User configuration structures */ +extern clock_manager_user_config_t const *g_clockManConfigsArr[]; + + + + +/*! @brief Count of user Callbacks */ +#define CLOCK_MANAGER_CALLBACK_CNT 0U + +/*! @brief Array of User callbacks */ +extern clock_manager_callback_user_config_t *g_clockManCallbacksArr[]; +#endif +/* ifndef clockMan1_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.1 [05.21] +** for the NXP C55 series of microcontrollers. +** +** ################################################################### +*/ + diff --git a/flexray_adapter/flexray_adapter/Generated_Code/dmaController1.c b/flexray_adapter/flexray_adapter/Generated_Code/dmaController1.c new file mode 100644 index 00000000000000..31591001a3ef77 --- /dev/null +++ b/flexray_adapter/flexray_adapter/Generated_Code/dmaController1.c @@ -0,0 +1,91 @@ +/* ################################################################### +** This component module is generated by Processor Expert. Do not modify it. +** Filename : dmaController1.c +** Project : flexray_adapter +** Processor : MPC5748G_176 +** Component : edma +** Version : Component SDK_MPC574x_06, Driver 01.00, CPU db: 3.00.000 +** Repository : SDK_MPC574x_06 +** Compiler : GNU C Compiler +** Date/Time : 2018-10-16, 17:49, # CodeGen: 1 +** +** Copyright 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All Rights Reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** ###################################################################*/ +/*! +** @file dmaController1.c +** @version 01.00 +*/ +/*! +** @addtogroup dmaController1_module dmaController1 module documentation +** @{ +*/ + +/* dmaController1. */ + +/* MODULE dmaController1. + * + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.7, External variable could be made static. + * The external variables will be used in other source files that user initialize + * to use this module. + */ + +#include "dmaController1.h" + +edma_state_t dmaController1_State; + +edma_chn_state_t dmaController1Chn0_State; + +edma_chn_state_t * const edmaChnStateArray[] = { + &dmaController1Chn0_State +}; + +edma_channel_config_t dmaController1Chn0_Config = { + .channelPriority = EDMA_CHN_DEFAULT_PRIORITY, + .virtChnConfig = EDMA_CHN0_NUMBER, + .source = EDMA_REQ_DISABLED_MUX0, + .callback = NULL, + .callbackParam = NULL +}; + +const edma_channel_config_t * const edmaChnConfigArray[] = { + &dmaController1Chn0_Config +}; + +const edma_user_config_t dmaController1_InitConfig0 = { + .chnArbitration = EDMA_ARBITRATION_FIXED_PRIORITY, + .groupArbitration = EDMA_ARBITRATION_FIXED_PRIORITY, + .groupPriority = EDMA_GRP0_PRIO_LOW_GRP1_PRIO_HIGH, + .haltOnError = false, +}; + + +/* END dmaController1. */ + +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.1 [05.21] +** for the NXP C55 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/flexray_adapter/flexray_adapter/Generated_Code/dmaController1.h b/flexray_adapter/flexray_adapter/Generated_Code/dmaController1.h new file mode 100644 index 00000000000000..01b21ef3a8dfee --- /dev/null +++ b/flexray_adapter/flexray_adapter/Generated_Code/dmaController1.h @@ -0,0 +1,122 @@ +/* ################################################################### +** This component module is generated by Processor Expert. Do not modify it. +** Filename : dmaController1.h +** Project : flexray_adapter +** Processor : MPC5748G_176 +** Component : edma +** Version : Component SDK_MPC574x_06, Driver 01.00, CPU db: 3.00.000 +** Repository : SDK_MPC574x_06 +** Compiler : GNU C Compiler +** Date/Time : 2018-10-16, 17:49, # CodeGen: 1 +** Contents : +** EDMA_DRV_Init - status_t EDMA_DRV_Init(edma_state_t *edmaState, const edma_user_config_t... +** EDMA_DRV_Deinit - status_t EDMA_DRV_Deinit(void); +** EDMA_DRV_ChannelInit - status_t EDMA_DRV_ChannelInit(edma_chn_state_t * edmaChannelState,const... +** EDMA_DRV_ReleaseChannel - status_t EDMA_DRV_ReleaseChannel(uint8_t virtualChannel); +** EDMA_DRV_StartChannel - status_t EDMA_DRV_StartChannel(uint8_t virtualChannel); +** EDMA_DRV_StopChannel - status_t EDMA_DRV_StopChannel(uint8_t virtualChannel); +** EDMA_DRV_InstallCallback - status_t EDMA_DRV_InstallCallback(uint8_t virtualChannel,edma_callback_t... +** EDMA_DRV_GetChannelStatus - edma_chn_status_t EDMA_DRV_GetChannelStatus(uint8_t virtualChannel); +** EDMA_DRV_PushConfigToReg - void EDMA_DRV_PushConfigToReg(uint8_t virtualChannel,edma_transfer_config_t *... +** EDMA_DRV_PushConfigToSTCD - void EDMA_DRV_PushConfigToSTCD(uint8_t virtualChannel,edma_transfer_config_t... +** EDMA_DRV_ConfigSingleBlockTransfer - status_t EDMA_DRV_ConfigSingleBlockTransfer(uint8_t... +** EDMA_DRV_ConfigLoopTransfer - status_t EDMA_DRV_ConfigLoopTransfer(uint8_t... +** EDMA_DRV_ConfigScatterGatherTransfer - status_t EDMA_DRV_ConfigScatterGatherTransfer(uint8_t... +** EDMA_DRV_ConfigMultiBlockTransfer - status_t EDMA_DRV_ConfigMultiBlockTransfer(uint8_t... +** EDMA_DRV_CancelTransfer - void EDMA_DRV_CancelTransfer(bool error); +** EDMA_DRV_SetChannelRequest - status_t EDMA_DRV_SetChannelRequest(uint8_t virtualChannel,... +** EDMA_DRV_ClearTCD - void EDMA_DRV_ClearTCD(uint8_t virtualChannel); +** EDMA_DRV_SetSrcAddr - void EDMA_DRV_SetSrcAddr(uint8_t virtualChannel, uint32_t address); +** EDMA_DRV_SetSrcOffset - void EDMA_DRV_SetSrcOffset(uint8_t virtualChannel, int16_t offset); +** EDMA_DRV_SetSrcReadChunkSize - void EDMA_DRV_SetSrcReadChunkSize(uint8_t virtualChannel,... +** EDMA_DRV_SetDestAddr - void EDMA_DRV_SetDestAddr(uint8_t virtualChannel, uint32_t address); +** EDMA_DRV_SetDestOffset - void EDMA_DRV_SetDestOffset(uint8_t virtualChannel, int16_t offset); +** EDMA_DRV_SetDestWriteChunkSize - void EDMA_DRV_SetDestWriteChunkSize(uint8_t virtualChannel,... +** EDMA_DRV_SetMinorLoopBlockSize - void EDMA_DRV_SetMinorLoopBlockSize(uint8_t virtualChannel, uint32_t nbytes); +** EDMA_DRV_SetMajorLoopIterationCount - void EDMA_DRV_SetMajorLoopIterationCount(uint8_t virtualChannel, uint32_t... +** EDMA_DRV_GetRemainingMajorIterationsCount - uint32_t EDMA_DRV_GetRemainingMajorIterationsCount(uint8_t virtualChannel); +** EDMA_DRV_SetScatterGatherLink - void EDMA_DRV_SetScatterGatherLink(uint8_t virtualChannel, uint32_t... +** EDMA_DRV_DisableRequestsOnTransferComplete - void EDMA_DRV_DisableRequestsOnTransferComplete(uint8_t virtualChannel, bool... +** EDMA_DRV_SetSrcLastAddrAdjustment - void EDMA_DRV_SetSrcLastAddrAdjustment(uint8_t virtualChannel, int32_t adjust); +** EDMA_DRV_SetDestLastAddrAdjustment - void EDMA_DRV_SetDestLastAddrAdjustment(uint8_t virtualChannel, int32_t adjust); +** EDMA_DRV_ConfigureInterrupt - void EDMA_DRV_ConfigureInterrupt(uint8_t virtualChannel,... +** EDMA_DRV_TriggerSwRequest - void EDMA_DRV_TriggerSwRequest(uint8_t virtualChannel); +** +** Copyright 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All Rights Reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** ###################################################################*/ +/*! +** @file dmaController1.h +** @version 01.00 +*/ +/*! +** @addtogroup dmaController1_module dmaController1 module documentation +** @{ +*/ + +/* MODULE dmaController1 + * + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. + * The macros are defined to be used by application code. + */ + +#ifndef dmaController1_H +#define dmaController1_H + +/* Include inherited beans */ +#include "clockMan1.h" +#include "Cpu.h" + +/*! @brief Physical channel number for channel configuration #0 */ +#define EDMA_CHN0_NUMBER 0U + +/*! @brief The total number of configured channels */ +#define EDMA_CONFIGURED_CHANNELS_COUNT 1U + +/*! @brief Driver state structure which holds driver runtime data */ +extern edma_state_t dmaController1_State; + +/*! @brief eDma channel state structure 0. Holds channel runtime data */ +extern edma_chn_state_t dmaController1Chn0_State; + +/*! @brief Array of channel state structures */ +extern edma_chn_state_t * const edmaChnStateArray[EDMA_CONFIGURED_CHANNELS_COUNT]; + +/*! @brief Configuration declaration */ +extern const edma_user_config_t dmaController1_InitConfig0; + +/*! @brief eDma channel configuration 0 */ +extern edma_channel_config_t dmaController1Chn0_Config; + +/*! @brief Array of channel configuration structures */ +extern const edma_channel_config_t * const edmaChnConfigArray[EDMA_CONFIGURED_CHANNELS_COUNT]; + +#endif /* ifndef dmaController1_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.1 [05.21] +** for the NXP C55 series of microcontrollers. +** +** ################################################################### +*/ + diff --git a/flexray_adapter/flexray_adapter/Generated_Code/linflexd_uart1.c b/flexray_adapter/flexray_adapter/Generated_Code/linflexd_uart1.c new file mode 100644 index 00000000000000..2f2c713f827cf2 --- /dev/null +++ b/flexray_adapter/flexray_adapter/Generated_Code/linflexd_uart1.c @@ -0,0 +1,81 @@ +/* ################################################################### +** This component module is generated by Processor Expert. Do not modify it. +** Filename : linflexd_uart1.c +** Project : flexray_adapter +** Processor : MPC5748G_176 +** Component : linflexd_uart +** Version : Component SDK_MPC574x_06, Driver 01.00, CPU db: 3.00.000 +** Repository : SDK_MPC574x_06 +** Compiler : GNU C Compiler +** Date/Time : 2018-10-16, 18:41, # CodeGen: 5 +** Abstract : +** +** +** Copyright 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All Rights Reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** ###################################################################*/ +/*! +** @file linflexd_uart1.c +** @version 01.00 +** @brief +** +*/ +/*! +** @addtogroup linflexd_uart1_module linflexd_uart1 module documentation +** @{ +*/ + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.7, External could be made static. + * The structures are defined for application use. + */ + +/* MODULE linflexd_uart1. */ + +#include "linflexd_uart1.h" + +/*! linflexd_uart1 configuration structure */ + +linflexd_uart_state_t linflexd_uart1_State; + +const linflexd_uart_user_config_t linflexd_uart1_InitConfig0 = { + .transferType = LINFLEXD_UART_USING_INTERRUPTS, + .baudRate = 115200U, + .parityCheck = false, + .parityType = LINFLEXD_UART_PARITY_EVEN, + .stopBitsCount = LINFLEXD_UART_ONE_STOP_BIT, + .wordLength = LINFLEXD_UART_8_BITS, + .rxDMAChannel = 0U, + .txDMAChannel = 0U, +}; + + +/* END linflexd_uart1. */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.1 [05.21] +** for the NXP C55 series of microcontrollers. +** +** ################################################################### +*/ + diff --git a/flexray_adapter/flexray_adapter/Generated_Code/linflexd_uart1.h b/flexray_adapter/flexray_adapter/Generated_Code/linflexd_uart1.h new file mode 100644 index 00000000000000..64649cd27175c3 --- /dev/null +++ b/flexray_adapter/flexray_adapter/Generated_Code/linflexd_uart1.h @@ -0,0 +1,96 @@ +/* ################################################################### +** This component module is generated by Processor Expert. Do not modify it. +** Filename : linflexd_uart1.h +** Project : flexray_adapter +** Processor : MPC5748G_176 +** Component : linflexd_uart +** Version : Component SDK_MPC574x_06, Driver 01.00, CPU db: 3.00.000 +** Repository : SDK_MPC574x_06 +** Compiler : GNU C Compiler +** Date/Time : 2018-10-16, 17:49, # CodeGen: 1 +** Abstract : +** +** Contents : +** LINFLEXD_UART_DRV_SetBaudRate - status_t LINFLEXD_UART_DRV_SetBaudRate(uint32_t instance,uint32_t baudrate); +** LINFLEXD_UART_DRV_GetBaudRate - status_t LINFLEXD_UART_DRV_GetBaudRate(uint32_t instance,uint32_t * baudrate); +** LINFLEXD_UART_DRV_Init - status_t LINFLEXD_UART_DRV_Init(uint32_t instance,linflexd_uart_state_t *... +** LINFLEXD_UART_DRV_Deinit - status_t LINFLEXD_UART_DRV_Deinit(uint32_t instance); +** LINFLEXD_UART_DRV_InstallRxCallback - uart_callback_t LINFLEXD_UART_DRV_InstallRxCallback(uint32_t... +** LINFLEXD_UART_DRV_InstallTxCallback - uart_callback_t LINFLEXD_UART_DRV_InstallTxCallback(uint32_t... +** LINFLEXD_UART_DRV_InstallErrorCallback - uart_callback_t LINFLEXD_UART_DRV_InstallErrorCallback(uint32_t... +** LINFLEXD_UART_DRV_SendDataBlocking - status_t LINFLEXD_UART_DRV_SendDataBlocking(uint32_t instance,const uint8_t *... +** LINFLEXD_UART_DRV_SendData - status_t LINFLEXD_UART_DRV_SendData(uint32_t instance,const uint8_t *... +** LINFLEXD_UART_DRV_GetTransmitStatus - status_t LINFLEXD_UART_DRV_GetTransmitStatus(uint32_t instance,uint32_t *... +** LINFLEXD_UART_DRV_AbortSendingData - status_t LINFLEXD_UART_DRV_AbortSendingData(uint32_t instance); +** LINFLEXD_UART_DRV_ReceiveDataBlocking - status_t LINFLEXD_UART_DRV_ReceiveDataBlocking(uint32_t instance,uint8_t *... +** LINFLEXD_UART_DRV_ReceiveData - status_t LINFLEXD_UART_DRV_ReceiveData(uint32_t instance,uint8_t *... +** LINFLEXD_UART_DRV_GetReceiveStatus - status_t LINFLEXD_UART_DRV_GetReceiveStatus(uint32_t instance,uint32_t *... +** LINFLEXD_UART_DRV_AbortReceivingData - status_t LINFLEXD_UART_DRV_AbortReceivingData(uint32_t instance); +** LINFLEXD_UART_DRV_SetTxBuffer - status_t LINFLEXD_UART_DRV_SetTxBuffer(uint32_t instance,const uint8_t *... +** LINFLEXD_UART_DRV_SetRxBuffer - status_t LINFLEXD_UART_DRV_SetRxBuffer(uint32_t instance,uint8_t *... +** +** Copyright 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All Rights Reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** ###################################################################*/ +/*! +** @file linflexd_uart1.h +** @version 01.00 +** @brief +** +*/ +/*! +** @addtogroup linflexd_uart1_module linflexd_uart1 module documentation +** @{ +*/ + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced + * The macro is defined for application use, mapping component name to device instance number. + */ + +#ifndef linflexd_uart1_H +#define linflexd_uart1_H +/* MODULE linflexd_uart1. */ +/* Include inherited beans */ +#include "clockMan1.h" +#include "dmaController1.h" +#include "Cpu.h" +#include "linflexd_uart_driver.h" + +/*! @brief Device instance number */ +#define INST_LINFLEXD_UART1 (4U) + +/*! Driver state structure */ +extern linflexd_uart_state_t linflexd_uart1_State; + +/*! @brief Configuration declaration */ +extern const linflexd_uart_user_config_t linflexd_uart1_InitConfig0; + +#endif /* ifndef linflexd_uart1_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.1 [05.21] +** for the NXP C55 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/flexray_adapter/flexray_adapter/Generated_Code/lwipcfg.h b/flexray_adapter/flexray_adapter/Generated_Code/lwipcfg.h new file mode 100644 index 00000000000000..90511dcd9c8fcc --- /dev/null +++ b/flexray_adapter/flexray_adapter/Generated_Code/lwipcfg.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_LWIPCFG_H +#define LWIP_LWIPCFG_H + +/**************************************************************************** + * FREERTOS + ****************************************************************************/ +/************************************* + * Raw applications + *************************************/ + +/************************************* + * Netconn applications + *************************************/ +#define LWIP_DNS_APP 0 +#define LWIP_SHELL_APP 0 + +/************************************* + * Socket applications + *************************************/ + +/**************************************************************************** + * ENET RX/TX BUFFER DESCRIPTOR + ****************************************************************************/ +#define ENET_RXBD_NUM 6 +#define ENET_TXBD_NUM 2 + +/**************************************************************************** + * MEDIA INDEPENDENT INTERFACE + ****************************************************************************/ +#define ENET_MIIMODE ENET_RMII_MODE +#define ENET_MIISPEED ENET_MII_SPEED_100M + +/**************************************************************************** + * ADDITIONAL USERS SETTINGS + ****************************************************************************/ + +#endif /* LWIP_LWIPCFG_H */ diff --git a/flexray_adapter/flexray_adapter/Generated_Code/lwipopts.h b/flexray_adapter/flexray_adapter/Generated_Code/lwipopts.h new file mode 100644 index 00000000000000..bca3e5bcb2f5a6 --- /dev/null +++ b/flexray_adapter/flexray_adapter/Generated_Code/lwipopts.h @@ -0,0 +1,291 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_LWIPOPTS_H +#define LWIP_LWIPOPTS_H + +/**************************************************************************** + * General: OS, Memory, etc. + ****************************************************************************/ +#define LWIP_NETIF_HOSTNAME 1 +#define LWIP_NETIF_HOSTNAME_TEXT ("tcpipBoard1") + +#define TCPIP_MBOX_SIZE 10 + +#define DEFAULT_UDP_RECVMBOX_SIZE 10 +#define DEFAULT_TCP_RECVMBOX_SIZE 10 +#define DEFAULT_RAW_RECVMBOX_SIZE 10 +#define DEFAULT_ACCEPTMBOX_SIZE 10 + +#define LWIP_NETIF_TX_SINGLE_PBUF 1 +#define LWIP_SUPPORT_CUSTOM_PBUF 1 +#define MEMP_USE_CUSTOM_POOLS 0 +#define MEM_USE_POOLS 0 + +/*! @brief OS options of the module */ +#define NO_SYS 0 /* 0: using OS with multi-thread --> can use raw, netconn or socket API*/ + +/*! @brief RAW API options of the module */ +#define LWIP_RAW 0 + +/*! @brief NETCONN API options of the module */ +#define LWIP_NETCONN 1 +#define LWIP_NETCONN_SEM_PER_THREAD (LWIP_NETCONN || LWIP_SOCKET) + +/*! @brief SOCKET API options of the module */ +#define LWIP_SOCKET 0 +#define LWIP_SOCKET_SET_ERRNO (LWIP_SOCKET) + + +/** SYS_LIGHTWEIGHT_PROT + * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection + * for certain critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#define SYS_LIGHTWEIGHT_PROT (NO_SYS==0) + +#define LWIP_SNMP LWIP_UDP +#define MIB2_STATS LWIP_SNMP +#define LWIP_DNS LWIP_UDP +#define LWIP_MDNS_RESPONDER LWIP_UDP +#define LWIP_NUM_NETIF_CLIENT_DATA (LWIP_MDNS_RESPONDER) +#define LWIP_HAVE_LOOPIF 0 +#define LWIP_NETIF_LOOPBACK 0 +#define TCP_LISTEN_BACKLOG 1 +#define LWIP_COMPAT_SOCKETS 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_TCPIP_CORE_LOCKING 1 +#define LWIP_NETIF_LINK_CALLBACK 0 +#define LWIP_NETIF_STATUS_CALLBACK 0 + +/*! @brief Memory options of the module */ +/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which + lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2 + byte alignment -> define MEM_ALIGNMENT to 2. */ +#define MEM_ALIGNMENT 4 + +/* MEM_SIZE: the size of the heap memory. If the application will send +a lot of data that needs to be copied, this should be set high. */ +#define MEM_SIZE 20480 + +/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application + sends a lot of data out of ROM (or other static memory), this + should be set high. */ +#define MEMP_NUM_PBUF 8 +/* MEMP_NUM_RAW_PCB: the number of UDP protocol control blocks. One + per active RAW "connection". */ +#define MEMP_NUM_RAW_PCB 4 +/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + per active UDP "connection". */ +#define MEMP_NUM_UDP_PCB 8 +/* MEMP_NUM_TCP_PCB: the number of simultaneously active TCP + connections. */ +#define MEMP_NUM_TCP_PCB 8 +/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP + connections. */ +#define MEMP_NUM_TCP_PCB_LISTEN 8 +/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP + segments. */ +#define MEMP_NUM_TCP_SEG 16 +/* MEMP_NUM_SYS_TIMEOUT: the number of simultaneously active + timeouts. */ +#define MEMP_NUM_SYS_TIMEOUT 15 + +/* The following four are used only with the sequential API and can be + set to 0 if the application only will use the raw API. */ +/* MEMP_NUM_NETBUF: the number of struct netbufs. */ +#define MEMP_NUM_NETBUF 16 +/* MEMP_NUM_NETCONN: the number of struct netconns. */ +#define MEMP_NUM_NETCONN 32 +/* MEMP_NUM_TCPIP_MSG_*: the number of struct tcpip_msg, which is used + for sequential API communication and incoming packets. Used in + src/api/tcpip.c. */ +#define MEMP_NUM_TCPIP_MSG_API 8 +#define MEMP_NUM_TCPIP_MSG_INPKT 8 + +#define PBUF_POOL_SIZE 0 /* The number of buffers in the pbuf pool. */ + +/**************************************************************************** + * Data Link Layer + ****************************************************************************/ +/*! @brief MAC address of the module */ +#ifndef LWIP_MAC_ADDR_BASE +#define LWIP_MAC_ADDR_BASE 0x22,0x33,0x44,0x55,0x66,0x77 +#endif /* ifndef LWIP_MAC_ADDR_BASE */ + +/*! @brief (LWIP_ETHERNET == 1) Enable ETHERNET support even though ARP might be disabled */ +#define LWIP_ETHERNET 1 + +/*! @brief ARP options */ +#define LWIP_ARP 1 /* 1: Enable ARP, 0: Disable ARP */ +#define ARP_TABLE_SIZE 10 /* ARP Table size */ +#define ARP_QUEUEING 0 /* ARP Queueing */ + +/**************************************************************************** + * IP Network Layer + ****************************************************************************/ +/*! @brief IPv4 options of the module */ +#define LWIP_IPV4 1 /* 1: Enable IPv4, 0: Disable IPv4 */ +/*! @brief Dynamic IP address settings of the module */ +#define LWIP_DHCP 0 /* 1: Enable DHCP, 0: Disable DHCP */ +#define DHCP_DOES_ARP_CHECK (LWIP_DHCP) /* 1: Do an ARP check on the offered address (recommended) */ +#define LWIP_AUTOIP 0 /* 1: Enable AUTOIP, 0: Disable AUTOIP */ +#define LWIP_DHCP_AUTOIP_COOP (LWIP_DHCP && LWIP_AUTOIP) /* AUTOIP and DHCP Cooperation */ +#define LWIP_DHCP_AUTOIP_COOP_TRIES 3 /* Number of DHCP Discover tries before switching to + AUTOIP. Set it to a low value will get a IP quickly. + But you should prepare to handle changing + IP address when DHCP overrides AUTOIP */ + +/*! @brief Static IP address settings of the module */ +#define LWIP_PORT_INIT_IPADDR(addr) IP4_ADDR((addr), 192,168,5,10) +#define LWIP_PORT_INIT_NETMASK(addr) IP4_ADDR((addr), 255,255,255,0) +#define LWIP_PORT_INIT_GW(addr) IP4_ADDR((addr), 192,168,5,1) + +/*! @brief IP forward ability of the module */ +#define IP_FORWARD 0 /* 1: Forward IP packets across network interfaces, + 0: Run lwIP on a device with only 1 network interface */ + +/*! @brief IP reassembly and segmentation. These are orthogonal even if they both deal with IP fragments */ +#define IP_REASSEMBLY 1 +#define IP_REASS_MAX_PBUFS 10 +#define MEMP_NUM_REASSDATA 10 +#define IP_FRAG 1 + +/*! @brief ICMP options of the module */ +#define LWIP_ICMP 1 +#define ICMP_TTL 255 /* ICMP Time to live value */ + +/*! @brief IGMP options of the module */ +#define LWIP_IGMP 0 + +/*! @brief IPv6 options of the module */ +#define LWIP_IPV6 0 /* 1: Enable IPv6, 0: Disable IPv6 */ + +/**************************************************************************** + * Transport Layer + ****************************************************************************/ +/*! @brief TCP options of the module */ +#define LWIP_TCP 1 /* 1: Enable TCP, 0: Disable TCP */ +#define TCP_TTL 255 /* TCP Time to live value */ +#define TCP_QUEUE_OOSEQ 0 /* Controls if TCP should queue segments that arrive out of order. + Defines to 0 if your device is low on memory. */ +#define TCP_MSS 1460 /* TCP Maximum segment size */ +#define TCP_SND_BUF 2920 /* TCP sender buffer space (bytes). */ + +/* TCP sender buffer space (pbufs). This must be at least = 2 * + TCP_SND_BUF/TCP_MSS for things to work. */ +#define TCP_SND_QUEUELEN (4 * TCP_SND_BUF/TCP_MSS) + +/* TCP writable space (bytes). This must be less than or equal + to TCP_SND_BUF. It is the amount of space which must be + available in the tcp snd_buf for select to return writable */ +#define TCP_SNDLOWAT (TCP_SND_BUF/2) + +#define TCP_WND 65535 /* TCP receive window. */ +#define TCP_MAXRTX 12 /* Maximum number of retransmissions of data segments. */ +#define TCP_SYNMAXRTX 4 /* Maximum number of retransmissions of SYN segments. */ + +/*! @brief UDP options of the module */ +#define LWIP_UDP 0 /* 1: Enable UDP, 0: Disable UDP */ + +/**************************************************************************** + * Debug, Statistics, PPP, Checksum + ****************************************************************************/ +/*! @brief Debugging options of the module */ +#ifdef LWIP_DEBUG +#define LWIP_DBG_MIN_LEVEL 0 +#define PPP_DEBUG LWIP_DBG_OFF +#define MEM_DEBUG LWIP_DBG_OFF +#define MEMP_DEBUG LWIP_DBG_OFF +#define PBUF_DEBUG LWIP_DBG_OFF +#define API_LIB_DEBUG LWIP_DBG_OFF +#define API_MSG_DEBUG LWIP_DBG_OFF +#define TCPIP_DEBUG LWIP_DBG_OFF +#define NETIF_DEBUG LWIP_DBG_OFF +#define SOCKETS_DEBUG LWIP_DBG_OFF +#define DNS_DEBUG LWIP_DBG_OFF +#define AUTOIP_DEBUG LWIP_DBG_OFF +#define DHCP_DEBUG LWIP_DBG_OFF +#define IP_DEBUG LWIP_DBG_OFF +#define IP_REASS_DEBUG LWIP_DBG_OFF +#define ICMP_DEBUG LWIP_DBG_OFF +#define IGMP_DEBUG LWIP_DBG_OFF +#define UDP_DEBUG LWIP_DBG_OFF +#define TCP_DEBUG LWIP_DBG_OFF +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#define TCP_WND_DEBUG LWIP_DBG_OFF +#define TCP_FR_DEBUG LWIP_DBG_OFF +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#define TCP_RST_DEBUG LWIP_DBG_OFF +#endif + +#define LWIP_DBG_TYPES_ON (LWIP_DBG_ON|LWIP_DBG_TRACE|LWIP_DBG_STATE|LWIP_DBG_FRESH|LWIP_DBG_HALT) + +/*! @brief Statistics options of the module */ +#define LWIP_STATS 1 /* 1: collect statistics; 0: not collect statistics */ +#define LWIP_STATS_DISPLAY 0 + +#if LWIP_STATS +#define LINK_STATS 1 +#define IP_STATS 1 +#define ICMP_STATS 1 +#define IGMP_STATS 1 +#define IPFRAG_STATS 1 +#define UDP_STATS 1 +#define TCP_STATS 1 +#define MEM_STATS 1 +#define MEMP_STATS 1 +#define PBUF_STATS 1 +#define SYS_STATS 1 +#endif /* LWIP_STATS */ + +/*! @brief PPP options of the module */ +#define PPP_SUPPORT 0 + +/*! @brief Checksum options of the module */ +#define LWIP_CHECKSUM_CTRL_PER_NETIF 0 +#define CHECKSUM_GEN_IP 0 +#define CHECKSUM_GEN_UDP 0 +#define CHECKSUM_GEN_TCP 0 +#define CHECKSUM_GEN_ICMP 0 +#define CHECKSUM_GEN_ICMP6 LWIP_IPV6 +#define CHECKSUM_CHECK_IP 0 +#define CHECKSUM_CHECK_UDP 0 +#define CHECKSUM_CHECK_TCP 0 +#define CHECKSUM_CHECK_ICMP 0 +#define CHECKSUM_CHECK_ICMP6 LWIP_IPV6 +#define LWIP_CHECKSUM_ON_COPY 0 + +#endif /* LWIP_LWIPOPTS_H */ diff --git a/flexray_adapter/flexray_adapter/Generated_Code/lwippools.h b/flexray_adapter/flexray_adapter/Generated_Code/lwippools.h new file mode 100644 index 00000000000000..1dc7c3b9ac56af --- /dev/null +++ b/flexray_adapter/flexray_adapter/Generated_Code/lwippools.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_LWIPPOOLS_H +#define LWIP_LWIPPOOLS_H + +/* OPTIONAL: Pools to replace heap allocation + * Optional: Pools can be used instead of the heap for mem_malloc. If + * so, these should be defined here, in increasing order according to + * the pool element size. + * + * LWIP_MALLOC_MEMPOOL(number_elements, element_size) + */ +#if MEM_USE_POOLS +LWIP_MALLOC_MEMPOOL_START +LWIP_MALLOC_MEMPOOL(100, 256) +LWIP_MALLOC_MEMPOOL(50, 512) +LWIP_MALLOC_MEMPOOL(20, 1024) +LWIP_MALLOC_MEMPOOL(20, 1536) +LWIP_MALLOC_MEMPOOL_END +#endif /* MEM_USE_POOLS */ + +/* Optional: Your custom pools can go here if you would like to use + * lwIP's memory pools for anything else. + */ + +#endif /* LWIP_LWIPPOOLS_H */ + diff --git a/flexray_adapter/flexray_adapter/Generated_Code/pin_mux.c b/flexray_adapter/flexray_adapter/Generated_Code/pin_mux.c new file mode 100644 index 00000000000000..e3c81a3209f78d --- /dev/null +++ b/flexray_adapter/flexray_adapter/Generated_Code/pin_mux.c @@ -0,0 +1,949 @@ +/* ################################################################### +** This component module is generated by Processor Expert. Do not modify it. +** Filename : pin_mux.c +** Project : flexray_adapter +** Processor : MPC5748G_176 +** Component : PinSettings +** Version : Component 1.2.0, Driver 1.4, CPU db: 3.00.000 +** Repository : SDK_MPC574x_06 +** Compiler : GNU C Compiler +** Date/Time : 2018-10-26, 16:36, # CodeGen: 11 +** Abstract : +** +** +** Copyright 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All Rights Reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** ###################################################################*/ +/*! +** @file pin_mux.c +** @version 1.4 +** @brief +** +*/ +/*! +** @addtogroup pin_mux_module pin_mux module documentation +** @{ +*/ + +/* MODULE pin_mux. */ +#include "device_registers.h" +#include "pin_mux.h" + +/** + * @page misra_violations MISRA-C:2012 violations + * + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed + * between a pointer to object and an integer type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed + * between pointer to void and an arithmetic type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.7, External variable could be made static. + * The external variables will be used in other source files in application code. + * + * @section [global] + * Violates MISRA 2012 Required Rule 9.3, partial array initialization. + * The object array is initialized sequentially. + * + * @section [global] + * Violates MISRA 2012 Required Rule 9.4, Duplicate initialization of object element. + * The object array is initialized sequentially. + * + */ + +/*! @brief Array of pin configuration structures */ +pin_settings_config_t g_pin_mux_InitConfigArr[NUM_OF_CONFIGURED_PINS] = +{ + { + .base = SIUL2, + .pinPortIdx = 25u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_ENABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTB, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_NO_INIT, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 24u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_ENABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTB, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_NO_INIT, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 48u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_ENABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTD, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_NO_INIT, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 49u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_ENABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTD, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_NO_INIT, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 50u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_ENABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTD, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_NO_INIT, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 51u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_ENABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTD, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_NO_INIT, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 52u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_ENABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTD, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_NO_INIT, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 53u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_ENABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTD, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_NO_INIT, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 54u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_ENABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTD, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_NO_INIT, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 55u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_ENABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTD, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_NO_INIT, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 56u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_ENABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTD, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_NO_INIT, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 20u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_ENABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTB, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_NO_INIT, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 3u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTA, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_ALT1, + .inputMuxReg[0] = 448, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 109u, + .mux = PORT_MUX_ALT4, + .outputBuffer = PORT_OUTPUT_BUFFER_ENABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = FULL_STRENGTH_WITHOUT_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_DISABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTG, + }, + { + .base = SIUL2, + .pinPortIdx = 108u, + .mux = PORT_MUX_ALT4, + .outputBuffer = PORT_OUTPUT_BUFFER_ENABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = FULL_STRENGTH_WITHOUT_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_DISABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTG, + }, + { + .base = SIUL2, + .pinPortIdx = 112u, + .mux = PORT_MUX_ALT3, + .outputBuffer = PORT_OUTPUT_BUFFER_ENABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = FULL_STRENGTH_WITHOUT_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_DISABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTH, + }, + { + .base = SIUL2, + .pinPortIdx = 113u, + .mux = PORT_MUX_ALT4, + .outputBuffer = PORT_OUTPUT_BUFFER_ENABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = FULL_STRENGTH_WITHOUT_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_DISABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTH, + }, + { + .base = SIUL2, + .pinPortIdx = 114u, + .mux = PORT_MUX_ALT4, + .outputBuffer = PORT_OUTPUT_BUFFER_ENABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = FULL_STRENGTH_WITHOUT_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_DISABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTH, + }, + { + .base = SIUL2, + .pinPortIdx = 115u, + .mux = PORT_MUX_ALT3, + .outputBuffer = PORT_OUTPUT_BUFFER_ENABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = FULL_STRENGTH_WITHOUT_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_DISABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTH, + }, + { + .base = SIUL2, + .pinPortIdx = 97u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = FULL_STRENGTH_WITHOUT_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTG, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_ALT1, + .inputMuxReg[0] = 449, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 96u, + .mux = PORT_MUX_ALT3, + .outputBuffer = PORT_OUTPUT_BUFFER_ENABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_DISABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTG, + }, + { + .base = SIUL2, + .pinPortIdx = 95u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTF, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_ALT1, + .inputMuxReg[0] = 457, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 94u, + .mux = PORT_MUX_ALT4, + .outputBuffer = PORT_OUTPUT_BUFFER_ENABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTF, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_ALT1, + .inputMuxReg[0] = 450, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 77u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTE, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_ALT1, + .inputMuxReg[0] = 454, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 7u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTA, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_ALT1, + .inputMuxReg[0] = 453, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 8u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTA, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_ALT1, + .inputMuxReg[0] = 452, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 9u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTA, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_ALT1, + .inputMuxReg[0] = 451, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 10u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTA, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_ALT1, + .inputMuxReg[0] = 456, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 11u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTA, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_ALT1, + .inputMuxReg[0] = 455, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 76u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTE, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_ALT1, + .inputMuxReg[0] = 458, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 5u, + .mux = PORT_MUX_ALT2, + .outputBuffer = PORT_OUTPUT_BUFFER_ENABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_DISABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTA, + }, + { + .base = SIUL2, + .pinPortIdx = 6u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTA, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_ALT1, + .inputMuxReg[0] = 204, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 66u, + .mux = PORT_MUX_ALT2, + .outputBuffer = PORT_OUTPUT_BUFFER_ENABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_DISABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTE, + }, + { + .base = SIUL2, + .pinPortIdx = 67u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTE, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_ALT1, + .inputMuxReg[0] = 224, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, + { + .base = SIUL2, + .pinPortIdx = 37u, + .mux = PORT_MUX_ALT4, + .outputBuffer = PORT_OUTPUT_BUFFER_ENABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_DISABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTC, + }, + { + .base = SIUL2, + .pinPortIdx = 36u, + .mux = PORT_MUX_ALT2, + .outputBuffer = PORT_OUTPUT_BUFFER_ENABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_DISABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTC, + }, + { + .base = SIUL2, + .pinPortIdx = 68u, + .mux = PORT_MUX_ALT3, + .outputBuffer = PORT_OUTPUT_BUFFER_ENABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_DISABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTE, + }, + { + .base = SIUL2, + .pinPortIdx = 69u, + .mux = PORT_MUX_AS_GPIO, + .outputBuffer = PORT_OUTPUT_BUFFER_DISABLED, + .openDrain = PORT_OPEN_DRAIN_DISABLED, + .slewRateCtrlSel = HALF_STRENGTH_WITH_SLEWRATE_CONTROL, + .hysteresisSelect = PORT_HYSTERESYS_DISABLED, + .safeMode = PORT_SAFE_MODE_DISABLED, + .analogPadCtrlSel = PORT_ANALOG_PAD_CONTROL_DISABLED, + .inputBuffer = PORT_INPUT_BUFFER_ENABLED, + .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, + .gpioBase = PTE, + .intConfig = + { + .intEdgeSel = SIUL2_INT_DISABLE + }, + .inputMux[0] = PORT_INPUT_MUX_ALT1, + .inputMuxReg[0] = 225, + .inputMux[1] = PORT_INPUT_MUX_NO_INIT, + .inputMux[2] = PORT_INPUT_MUX_NO_INIT, + .inputMux[3] = PORT_INPUT_MUX_NO_INIT, + .inputMux[4] = PORT_INPUT_MUX_NO_INIT, + .inputMux[5] = PORT_INPUT_MUX_NO_INIT, + .inputMux[6] = PORT_INPUT_MUX_NO_INIT, + .inputMux[7] = PORT_INPUT_MUX_NO_INIT, + }, +}; + +/* END pin_mux. */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.1 [05.21] +** for the NXP C55 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/flexray_adapter/flexray_adapter/Generated_Code/pin_mux.h b/flexray_adapter/flexray_adapter/Generated_Code/pin_mux.h new file mode 100644 index 00000000000000..bf37964bc616cb --- /dev/null +++ b/flexray_adapter/flexray_adapter/Generated_Code/pin_mux.h @@ -0,0 +1,3193 @@ +/* ################################################################### +** This component module is generated by Processor Expert. Do not modify it. +** Filename : pin_mux.h +** Project : flexray_adapter +** Processor : MPC5748G_176 +** Component : PinSettings +** Version : Component 1.2.0, Driver 1.4, CPU db: 3.00.000 +** Repository : SDK_MPC574x_06 +** Compiler : GNU C Compiler +** Date/Time : 2018-10-26, 16:36, # CodeGen: 11 +** Abstract : +** +** Settings : +** Component name : pin_mux +** PinSettings IP Block : PinSettings +** Processor : MPC5748G_176 +** Pin settings : +** Routing : +** Peripheral Type ADC : +** Custom name : ADC_0 +** ADC_0 : +** ADC MA 0 : +** ADC MA 1 : +** ADC MA 2 : +** Standard Channel 0 : PB[8] +** Standard Channel 1 : PB[9] +** Standard Channel 2 : +** Standard Channel 3 : +** Standard Channel 4 : +** Standard Channel 5 : +** Standard Channel 6 : +** Standard Channel 7 : +** Standard Channel 8 : +** Standard Channel 9 : +** Standard Channel 10 : +** Standard Channel 11 : +** Standard Channel 12 : +** Standard Channel 13 : +** Standard Channel 14 : +** Standard Channel 15 : +** Standard Channel 16 : +** Standard Channel 19 : +** Standard Channel 20 : +** Standard Channel 21 : +** Standard Channel 22 : +** Standard Channel 23 : +** Standard Channel 24 : +** Standard Channel 25 : +** Standard Channel 26 : +** Standard Channel 27 : +** External Channel 0 : +** External Channel 1 : +** External Channel 2 : +** External Channel 3 : +** Custom name : ADC_1 +** ADC_1 : +** ADC MA 0 : +** ADC MA 1 : +** ADC MA 2 : +** Precision Channel 0 : PB[4] +** Precision Channel 1 : +** Precision Channel 2 : +** Precision Channel 3 : +** Precision Channel 4 : PD[0] +** Precision Channel 5 : PD[1] +** Precision Channel 6 : PD[2] +** Precision Channel 7 : PD[3] +** Precision Channel 8 : PD[4] +** Precision Channel 9 : PD[5] +** Precision Channel 10 : PD[6] +** Precision Channel 11 : PD[7] +** Precision Channel 12 : PD[8] +** Precision Channel 13 : +** Precision Channel 14 : +** Standard Channel 0 : +** Standard Channel 1 : +** Standard Channel 2 : +** Standard Channel 3 : +** Standard Channel 4 : +** Standard Channel 5 : +** Standard Channel 6 : +** Standard Channel 7 : +** Standard Channel 8 : +** Standard Channel 9 : +** Standard Channel 10 : +** Standard Channel 11 : +** Standard Channel 12 : +** Standard Channel 13 : +** External Channel 0 : +** External Channel 1 : +** External Channel 2 : +** External Channel 3 : +** Peripheral Type AIPS : +** Custom name : AIPS_A +** Custom name : AIPS_B +** Peripheral Type AXBS : +** Custom name : AXBS_0 +** Custom name : AXBS_1 +** Peripheral Type BCTU : +** Custom name : BCTU +** Peripheral Type C55FMC : +** Custom name : C55FMC +** Peripheral Type CAN : +** Custom name : CAN_0 +** CAN_0 : +** Receiver Input : +** CAN_0: Receiver Input : +** Transmitter Output : +** Custom name : CAN_1 +** CAN_1 : +** Receiver Input : +** CAN_1: Receiver Input : +** Transmitter Output : +** Custom name : CAN_2 +** CAN_2 : +** Receiver Input : +** CAN_2: Receiver Input : +** Transmitter Output : +** Custom name : CAN_3 +** CAN_3 : +** Receiver Input : +** CAN_3: Receiver Input : +** Transmitter Output : +** Custom name : CAN_4 +** CAN_4 : +** Receiver Input : +** CAN_4: Receiver Input : +** Transmitter Output : +** Custom name : CAN_5 +** CAN_5 : +** Receiver Input : +** CAN_5: Receiver Input : +** Transmitter Output : +** Custom name : CAN_6 +** CAN_6 : +** Receiver Input : +** CAN_6: Receiver Input : +** Transmitter Output : +** Custom name : CAN_7 +** CAN_7 : +** Receiver Input : +** CAN_7: Receiver Input : +** Transmitter Output : +** Peripheral Type CMP : +** Custom name : CMP_0 +** CMP_0 : +** Input 0 : +** Input 1 : +** Input 2 : +** Input 3 : +** Input 4 : +** Input 5 : +** Input 6 : +** Input 7 : +** Output 2 : +** Custom name : CMP_1 +** CMP_1 : +** Input 8 : +** Input 9 : +** Input 10 : +** Input 11 : +** Input 12 : +** Input 13 : +** Input 14 : +** Input 15 : +** Output 2 : +** Custom name : CMP_2 +** CMP_2 : +** Input 16 : +** Input 17 : +** Input 18 : +** Input 19 : +** Input 20 : +** Input 21 : +** Input 22 : +** Input 23 : +** Output 2 : +** Peripheral Type CMU : +** Custom name : CMU +** Peripheral Type CRC : +** Custom name : CRC +** Peripheral Type DCI : +** DCI : +** Test Clock : +** Test Data Input : +** Test Data Output : +** Test Mode Select : +** Direction : +** Peripheral Type DMA : +** Custom name : DMA +** Peripheral Type DMAMUX : +** Custom name : DMAMUX_0 +** Custom name : DMAMUX_1 +** Peripheral Type DSPI : +** Custom name : DSPI_0 +** DSPI_0 : +** Chip Select Output 0 : +** Chip Select Output 1 : +** Chip Select Output 2 : +** Chip Select Output 3 : +** Chip Select Output 4 : +** Chip Select Output 5 : +** Serial Clock Output : +** DSPI_0: Serial Clock Output : +** Direction : +** Serial Data Input : +** DSPI_0: Serial Data Input : +** Serial Data Output : +** Slave Select Input : +** DSPI_0: Slave Select Input : +** Custom name : DSPI_1 +** DSPI_1 : +** Chip Select Output 0 : +** Chip Select Output 1 : +** Chip Select Output 2 : +** Chip Select Output 3 : +** Chip Select Output 4 : +** Serial Clock Output : +** DSPI_1: Serial Clock Output : +** Direction : +** Serial Data Input : +** DSPI_1: Serial Data Input : +** Serial Data Output : +** Slave Select Input : +** DSPI_1: Slave Select Input : +** Custom name : DSPI_2 +** DSPI_2 : +** Chip Select Output 0 : +** Chip Select Output 1 : +** Chip Select Output 2 : +** Chip Select Output 3 : +** Serial Clock Output : +** DSPI_2: Serial Clock Output : +** Direction : +** Serial Data Input : +** DSPI_2: Serial Data Input : +** Serial Data Output : +** Slave Select Input : +** DSPI_2: Slave Select Input : +** Custom name : DSPI_3 +** DSPI_3 : +** Chip Select Output 0 : +** Chip Select Output 1 : +** Serial Clock Output : +** DSPI_3: Serial Clock Output : +** Direction : +** Serial Data Input : +** DSPI_3: Serial Data Input : +** Serial Data Output : +** Slave Select Input : +** DSPI_3: Slave Select Input : +** Peripheral Type ENET : +** Custom name : ENET_0 +** ENET_0 : +** ENET Timer 0 : +** ENET_0: ENET Timer 0 : +** ENET Timer 1 : +** ENET_0: ENET Timer 1 : +** ENET0 Collision : PA[10] +** ENET_0: ENET0 Collision : +** ENET0 Carrier Sense : PE[12] +** ENET_0: ENET0 Carrier Sense : +** ENET0 MII Receive Clock : PA[3] +** ENET_0: ENET0 MII Receive Clock : +** ENET MII Receive Data 2 : PA[7] +** ENET_0: ENET MII Receive Data 2 : +** ENET MII Receive Data 3 : PE[13] +** ENET_0: ENET MII Receive Data 3 : +** ENET MII Transmit Data 2 : PG[12] +** ENET MII Transmit Data 3 : PG[13] +** ENET0 MII Transmit Error : PH[3] +** ENET0 RMII Management Data Clock : PG[0] +** ENET0 RMII Management Data Input/Output: PF[14] +** ENET_0: ENET0 RMII Management Data Input/Output: +** ENET0 RMII Receive Data 0 : PA[9] +** ENET_0: ENET0 RMII Receive Data 0 : +** ENET0 RMII Receive Data 1 : PA[8] +** ENET_0: ENET0 RMII Receive Data 1 : +** ENET0 RMII Receive Data Valid : PF[15] +** ENET_0: ENET0 RMII Receive Data Valid : +** ENET0 RMII Receive Error : PA[11] +** ENET_0: ENET0 RMII Receive Error : +** ENET0 RMII Transmit Clock : PG[1] +** ENET_0: ENET0 RMII Transmit Clock : +** Direction : Input +** ENET0 RMII Transmit Data 0 : PH[1] +** ENET0 RMII Transmit Data 1 : PH[0] +** ENET0 RMII Transmit Enable : PH[2] +** Custom name : ENET_1 +** ENET_1 : +** ENET Timer 0 : +** ENET_1: ENET Timer 0 : +** ENET Timer 1 : +** ENET_1: ENET Timer 1 : +** ENET1 MII Receive Clock : +** ENET_1: ENET1 MII Receive Clock : +** ENET1 MII Receive Data 0 : +** ENET_1: ENET1 MII Receive Data 0 : +** ENET1 MII Receive Data 1 : +** ENET_1: ENET1 MII Receive Data 1 : +** ENET MII Receive Data 2 : +** ENET_1: ENET MII Receive Data 2 : +** ENET MII Receive Data 3 : +** ENET_1: ENET MII Receive Data 3 : +** ENET1 MII Receive Data Valid : +** ENET_1: ENET1 MII Receive Data Valid : +** ENET1 MII Transmit Clock : +** ENET_1: ENET1 MII Transmit Clock : +** ENET1 MII Transmit Data 0 : +** ENET1 MII Transmit Data 1 : +** ENET MII Transmit Data 2 : +** ENET MII Transmit Data 3 : +** ENET1 MII Transmit Enable : +** Peripheral Type ESW : +** Custom name : ESW_0 +** Custom name : ESW_1 +** Peripheral Type FCCU : +** Custom name : FCCU +** FCCU : +** Error Input : +** FCCU: Error Input : +** Output : +** Direction : +** Output : +** Direction : +** Peripheral Type FIRC : +** Custom name : FIRC +** Peripheral Type FR : +** Custom name : FR +** Peripheral Type FlexRay : +** FlexRay : +** Debug 0 : +** Debug 1 : +** Debug 2 : +** Debug 3 : +** Receive Data Channel A : PE[3] +** FlexRay: Receive Data Channel A : +** Receive Data Channel B : PE[5] +** FlexRay: Receive Data Channel B : +** Transmit Data Channel A : PC[5] +** Transmit Data Channel B : PE[4] +** Transmit Enable A : PE[2] +** Transmit Enable B : PC[4] +** Peripheral Type GPR : +** Custom name : GPR +** Peripheral Type HSM : +** HSM : +** Data 0 : +** Data 1 : +** Peripheral Type I2C : +** Custom name : I2C_0 +** I2C_0 : +** Serial Clock : +** I2C_0: Serial Clock : +** Data : +** I2C_0: Data : +** Custom name : I2C_1 +** I2C_1 : +** Serial Clock : +** I2C_1: Serial Clock : +** Data : +** I2C_1: Data : +** Custom name : I2C_2 +** I2C_2 : +** Serial Clock : +** I2C_2: Serial Clock : +** Data : +** I2C_2: Data : +** Custom name : I2C_3 +** I2C_3 : +** Serial Clock : +** I2C_3: Serial Clock : +** Data : +** I2C_3: Data : +** Peripheral Type I2S : +** Custom name : I2S_0 +** Custom name : I2S_1 +** Custom name : I2S_2 +** Peripheral Type INTC : +** Custom name : INTC +** Peripheral Type JDC : +** Custom name : JDC +** Peripheral Type LINFlexD : +** Custom name : LINFlexD_0 +** LINFlexD_0 : +** Receive Data : +** LINFlexD_0: Receive Data : +** Transmit Data : +** Custom name : LINFlexD_1 +** LINFlexD_1 : +** Receive Data : +** LINFlexD_1: Receive Data : +** Transmit Data : +** Custom name : LINFlexD_2 +** LINFlexD_2 : +** Receive Data : +** LINFlexD_2: Receive Data : +** Transmit Data : +** Custom name : LINFlexD_3 +** LINFlexD_3 : +** Receive Data : +** LINFlexD_3: Receive Data : +** Transmit Data : +** Custom name : LINFlexD_4 +** LINFlexD_4 : +** Receive Data : PA[6] +** LINFlexD_4: Receive Data : +** Transmit Data : PA[5] +** Custom name : LINFlexD_5 +** LINFlexD_5 : +** Receive Data : +** LINFlexD_5: Receive Data : +** Transmit Data : +** Custom name : LINFlexD_6 +** LINFlexD_6 : +** Receive Data : +** LINFlexD_6: Receive Data : +** Transmit Data : +** Custom name : LINFlexD_7 +** LINFlexD_7 : +** Receive Data : +** LINFlexD_7: Receive Data : +** Transmit Data : +** Custom name : LINFlexD_8 +** LINFlexD_8 : +** Receive Data : +** LINFlexD_8: Receive Data : +** Transmit Data : +** Custom name : LINFlexD_9 +** LINFlexD_9 : +** Receive Data : +** LINFlexD_9: Receive Data : +** Transmit Data : +** Custom name : LINFlexD_10 +** LINFlexD_10 : +** Receive Data : +** LINFlexD_10: Receive Data : +** Transmit Data : +** Custom name : LINFlexD_11 +** LINFlexD_11 : +** Receive Data : +** LINFlexD_11: Receive Data : +** Transmit Data : +** Custom name : LINFlexD_12 +** LINFlexD_12 : +** Custom name : LINFlexD_13 +** LINFlexD_13 : +** Custom name : LINFlexD_14 +** LINFlexD_14 : +** Custom name : LINFlexD_15 +** LINFlexD_15 : +** Custom name : LINFlexD_16 +** LINFlexD_16 : +** Custom name : LINFlexD_17 +** LINFlexD_17 : +** Peripheral Type LPU : +** Custom name : LPU +** Peripheral Type MC_CGM : +** Custom name : MC_CGM +** Peripheral Type MC_ME : +** Custom name : MC_ME +** Peripheral Type MC_PCU : +** Custom name : MC_PCU +** Peripheral Type MC_RGM : +** Custom name : MC_RGM +** Peripheral Type MEMU : +** Custom name : MEMU_0 +** Custom name : MEMU_1 +** Peripheral Type MLB : +** Custom name : MLB +** MLB : +** Clock Input : +** MLB: Clock Input : +** Data Input : +** MLB: Data Input : +** Direction : +** Signal Input : +** MLB: Signal Input : +** Direction : +** Peripheral Type PASS : +** Custom name : PASS +** Peripheral Type PCM : +** Custom name : PCM +** Peripheral Type PFLASH : +** Custom name : PFLASH +** Peripheral Type PIT : +** Custom name : PIT +** Peripheral Type PLLDIG : +** Custom name : PLLDIG +** Peripheral Type PMCDIG : +** Custom name : PMCDIG +** Peripheral Type PRAMC : +** Custom name : PRAMC_0 +** Custom name : PRAMC_1 +** Custom name : PRAMC_2 +** Peripheral Type Platform : +** Platform : +** Clock Output : +** Clock Output : +** External Regulator Control : +** Power On Reset Input/Output : PORST +** Hard Reset Input/Ouput : RESET +** Direction : +** Peripheral Type PowerAndGround : +** PowerAndGround : +** SAR ADC 1 Reference High Input : VDD_HV_ADC1_REF +** Core Logic Low Voltage Supply : VDD_LV +** Peripheral Type RTC : +** Custom name : RTC +** Peripheral Type SAI : +** SAI_0 : +** Bit Clock : +** SAI_0: Bit Clock : +** Data 0 : +** SAI_0: Data 0 : +** Data 1 : +** SAI_0: Data 1 : +** Data 2 : +** SAI_0: Data 2 : +** Data 3 : +** SAI_0: Data 3 : +** Audio Master Clock : +** SAI_0: Audio Master Clock : +** Frame Sync : +** SAI_0: Frame Sync : +** SAI_1 : +** Bit Clock : +** SAI_1: Bit Clock : +** Data 0 : +** SAI_1: Data 0 : +** Audio Master Clock : +** SAI_1: Audio Master Clock : +** Frame Sync : +** SAI_1: Frame Sync : +** SAI_2 : +** Bit Clock : +** SAI_2: Bit Clock : +** Data 0 : +** SAI_2: Data 0 : +** Audio Master Clock : +** SAI_2: Audio Master Clock : +** Frame Sync : +** SAI_2: Frame Sync : +** Peripheral Type SEMA42 : +** Custom name : SEMA42 +** Peripheral Type SIRC : +** Custom name : SIRC +** Peripheral Type SIUL2 : +** Custom name : SIUL2 +** SIUL2 : +** External interrupt 0 : +** External interrupt 0 : +** External interrupt 1 : +** External interrupt 1 : +** External interrupt 2 : +** External interrupt 2 : +** External interrupt 3 : +** External interrupt 3 : +** External interrupt 4 : +** External interrupt 4 : +** External interrupt 5 : +** External interrupt 5 : +** External interrupt 6 : +** External interrupt 6 : +** External interrupt 7 : +** External interrupt 7 : +** External interrupt 8 : +** External interrupt 8 : +** External interrupt 9 : +** External interrupt 9 : +** External interrupt 10 : +** External interrupt 10 : +** External interrupt 11 : +** External interrupt 11 : +** External interrupt 12 : +** External interrupt 12 : +** External interrupt 13 : +** External interrupt 13 : +** External interrupt 14 : +** External interrupt 14 : +** External interrupt 15 : +** External interrupt 15 : +** External interrupt 16 : +** External interrupt 16 : +** External interrupt 17 : +** External interrupt 17 : +** External interrupt 18 : +** External interrupt 18 : +** External interrupt 19 : +** External interrupt 19 : +** External interrupt 20 : +** External interrupt 20 : +** External interrupt 21 : +** External interrupt 21 : +** External interrupt 22 : +** External interrupt 22 : +** External interrupt 23 : +** External interrupt 23 : +** GPI 20 : PB[4] +** GPI 21 : +** GPI 22 : +** GPI 23 : +** GPI 24 : PB[8] +** GPI 25 : PB[9] +** GPI 48 : PD[0] +** GPI 49 : PD[1] +** GPI 50 : PD[2] +** GPI 51 : PD[3] +** GPI 52 : PD[4] +** GPI 53 : PD[5] +** GPI 54 : PD[6] +** GPI 55 : PD[7] +** GPI 56 : PD[8] +** GPI 57 : +** GPI 58 : +** GPIO 0 : +** Direction : +** GPIO 1 : +** Direction : +** GPIO 2 : +** Direction : +** GPIO 3 : +** Direction : +** GPIO 4 : +** Direction : +** GPIO 5 : +** Direction : +** GPIO 6 : +** Direction : +** GPIO 7 : +** Direction : +** GPIO 8 : +** Direction : +** GPIO 9 : +** Direction : +** GPIO 10 : +** Direction : +** GPIO 11 : +** Direction : +** GPIO 12 : +** Direction : +** GPIO 13 : +** Direction : +** GPIO 14 : +** Direction : +** GPIO 15 : +** Direction : +** GPIO 16 : +** Direction : +** GPIO 17 : +** Direction : +** GPIO 18 : +** Direction : +** GPIO 19 : +** Direction : +** GPIO 26 : +** Direction : +** GPIO 27 : +** Direction : +** GPIO 28 : +** Direction : +** GPIO 29 : +** Direction : +** GPIO 30 : +** Direction : +** GPIO 31 : +** Direction : +** GPIO 32 : +** Direction : +** GPIO 33 : +** Direction : +** GPIO 34 : +** Direction : +** GPIO 35 : +** Direction : +** GPIO 36 : +** Direction : +** GPIO 37 : +** Direction : +** GPIO 38 : +** Direction : +** GPIO 39 : +** Direction : +** GPIO 40 : +** Direction : +** GPIO 41 : +** Direction : +** GPIO 42 : +** Direction : +** GPIO 43 : +** Direction : +** GPIO 44 : +** Direction : +** GPIO 45 : +** Direction : +** GPIO 46 : +** Direction : +** GPIO 47 : +** Direction : +** GPIO 60 : +** Direction : +** GPIO 61 : +** Direction : +** GPIO 62 : +** Direction : +** GPIO 63 : +** Direction : +** GPIO 64 : +** Direction : +** GPIO 65 : +** Direction : +** GPIO 66 : +** Direction : +** GPIO 67 : +** Direction : +** GPIO 68 : +** Direction : +** GPIO 69 : +** Direction : +** GPIO 70 : +** Direction : +** GPIO 71 : +** Direction : +** GPIO 72 : +** Direction : +** GPIO 73 : +** Direction : +** GPIO 74 : +** Direction : +** GPIO 75 : +** Direction : +** GPIO 76 : +** Direction : +** GPIO 77 : +** Direction : +** GPIO 78 : +** Direction : +** GPIO 79 : +** Direction : +** GPIO 80 : +** Direction : +** GPIO 81 : +** Direction : +** GPIO 82 : +** Direction : +** GPIO 83 : +** Direction : +** GPIO 84 : +** Direction : +** GPIO 85 : +** Direction : +** GPIO 86 : +** Direction : +** GPIO 87 : +** Direction : +** GPIO 88 : +** Direction : +** GPIO 89 : +** Direction : +** GPIO 90 : +** Direction : +** GPIO 91 : +** Direction : +** GPIO 92 : +** Direction : +** GPIO 93 : +** Direction : +** GPIO 94 : +** Direction : +** GPIO 95 : +** Direction : +** GPIO 96 : +** Direction : +** GPIO 97 : +** Direction : +** GPIO 98 : +** Direction : +** GPIO 99 : +** Direction : +** GPIO 100 : +** Direction : +** GPIO 101 : +** Direction : +** GPIO 102 : +** Direction : +** GPIO 103 : +** Direction : +** GPIO 104 : +** Direction : +** GPIO 105 : +** Direction : +** GPIO 106 : +** Direction : +** GPIO 107 : +** Direction : +** GPIO 108 : +** Direction : +** GPIO 109 : +** Direction : +** GPIO 110 : +** Direction : +** GPIO 111 : +** Direction : +** GPIO 112 : +** Direction : +** GPIO 113 : +** Direction : +** GPIO 114 : +** Direction : +** GPIO 115 : +** Direction : +** GPIO 116 : +** Direction : +** GPIO 117 : +** Direction : +** GPIO 118 : +** Direction : +** GPIO 119 : +** Direction : +** GPIO 120 : +** Direction : +** GPIO 121 : +** Direction : +** GPIO 122 : +** Direction : +** GPIO 123 : +** Direction : +** GPIO 124 : +** Direction : +** GPIO 125 : +** Direction : +** GPIO 126 : +** Direction : +** GPIO 127 : +** Direction : +** GPIO 128 : +** Direction : +** GPIO 129 : +** Direction : +** GPIO 130 : +** Direction : +** GPIO 131 : +** Direction : +** GPIO 132 : +** Direction : +** GPIO 133 : +** Direction : +** GPIO 134 : +** Direction : +** GPIO 135 : +** Direction : +** GPIO 136 : +** Direction : +** GPIO 139 : +** Direction : +** GPIO 140 : +** Direction : +** GPIO 141 : +** Direction : +** GPIO 142 : +** Direction : +** GPIO 143 : +** Direction : +** GPIO 144 : +** Direction : +** GPIO 145 : +** Direction : +** GPIO 146 : +** Direction : +** GPIO 147 : +** Direction : +** GPIO 148 : +** Direction : +** Peripheral Type SMPU : +** Custom name : SMPU_0 +** Custom name : SMPU_1 +** Peripheral Type SPI : +** Custom name : SPI_0 +** SPI_0 : +** Chip Select Output 0 : +** Chip Select Output 1 : +** Chip Select Output 2 : +** Chip Select Output 3 : +** Serial Clock Output : +** SPI_0: Serial Clock Output : +** Direction : +** Serial Data Input : +** SPI_0: Serial Data Input : +** Serial Data Output : +** Slave Select Input : +** SPI_0: Slave Select Input : +** Custom name : SPI_1 +** SPI_1 : +** Chip Select Output 0 : +** Chip Select Output 1 : +** Chip Select Output 2 : +** Serial Clock Output : +** SPI_1: Serial Clock Output : +** Direction : +** Serial Data Input : +** SPI_1: Serial Data Input : +** Serial Data Output : +** Slave Select Input : +** SPI_1: Slave Select Input : +** Custom name : SPI_2 +** SPI_2 : +** Chip Select Output 0 : +** Chip Select Output 1 : +** Chip Select Output 2 : +** Serial Clock Output : +** SPI_2: Serial Clock Output : +** Direction : +** Serial Data Input : +** SPI_2: Serial Data Input : +** Serial Data Output : +** Slave Select Input : +** SPI_2: Slave Select Input : +** Custom name : SPI_3 +** SPI_3 : +** Chip Select Output 0 : +** Chip Select Output 1 : +** Serial Clock Output : +** SPI_3: Serial Clock Output : +** Direction : +** Serial Data Input : +** SPI_3: Serial Data Input : +** Serial Data Output : +** Slave Select Input : +** SPI_3: Slave Select Input : +** Custom name : SPI_4 +** SPI_4 : +** Chip Select Output 0 : +** Serial Clock Output : +** SPI_4: Serial Clock Output : +** Direction : +** Serial Data Input : +** SPI_4: Serial Data Input : +** Serial Data Output : +** Slave Select Input : +** SPI_4: Slave Select Input : +** Custom name : SPI_5 +** SPI_5 : +** Chip Select Output 0 : +** Serial Clock Output : +** SPI_5: Serial Clock Output : +** Direction : +** Serial Data Input : +** SPI_5: Serial Data Input : +** Serial Data Output : +** Slave Select Input : +** SPI_5: Slave Select Input : +** Peripheral Type SSCM : +** Custom name : SSCM +** SSCM : +** SSCM Debug Data 0 : +** SSCM Debug Data 1 : +** SSCM Debug Data 2 : +** SSCM Debug Data 3 : +** SSCM Debug Data 4 : +** SSCM Debug Data 5 : +** SSCM Debug Data 6 : +** SSCM Debug Data 7 : +** Peripheral Type STCU2 : +** Custom name : STCU2 +** Peripheral Type STM : +** Custom name : STM_0 +** Custom name : STM_1 +** Custom name : STM_2 +** Peripheral Type SWT : +** Custom name : SWT_0 +** Custom name : SWT_1 +** Custom name : SWT_2 +** Peripheral Type SXOSC : +** Custom name : SXOSC +** Peripheral Type TDM : +** Custom name : TDM +** Peripheral Type UHST : +** Custom name : UHST +** Peripheral Type UHSTNC : +** Custom name : UHSTNC +** Peripheral Type UOTG : +** Custom name : UOTG +** Peripheral Type UOTGNC : +** Custom name : UOTGNC +** Peripheral Type USB : +** USB_0 : +** Clock : +** USB_0: Clock : +** Data Bit : +** USB_0: Data Bit : +** Data Bit : +** USB_0: Data Bit : +** Data Bit : +** USB_0: Data Bit : +** Data Bit : +** USB_0: Data Bit : +** Data Bit : +** USB_0: Data Bit : +** Data Bit : +** USB_0: Data Bit : +** Data Bit : +** USB_0: Data Bit : +** Data Bit : +** USB_0: Data Bit : +** Bus Direction : +** USB_0: Bus Direction : +** Fault : +** USB_0: Fault : +** Next Data : +** USB_0: Next Data : +** Stop : +** USB_1 : +** Clock : +** USB_1: Clock : +** Data Bit : +** USB_1: Data Bit : +** Data Bit : +** USB_1: Data Bit : +** Data Bit : +** USB_1: Data Bit : +** Data Bit : +** USB_1: Data Bit : +** Data Bit : +** USB_1: Data Bit : +** Data Bit : +** USB_1: Data Bit : +** Data Bit : +** USB_1: Data Bit : +** Data Bit : +** USB_1: Data Bit : +** Bus Direction : +** USB_1: Bus Direction : +** Fault : +** USB_1: Fault : +** Next Data : +** USB_1: Next Data : +** Stop : +** Peripheral Type WKPU : +** Custom name : WKPU +** WKPU : +** Interrupt Source 2 : +** Interrupt Source 3 : +** Interrupt Source 4 : +** Interrupt Source 5 : +** Interrupt Source 6 : +** Interrupt Source 7 : +** Interrupt Source 8 : +** Interrupt Source 9 : +** Interrupt Source 10 : +** Interrupt Source 11 : +** Interrupt Source 12 : +** Interrupt Source 13 : +** Interrupt Source 14 : +** Interrupt Source 15 : +** Interrupt Source 16 : +** Interrupt Source 17 : +** Interrupt Source 18 : +** Interrupt Source 19 : +** Interrupt Source 20 : +** Interrupt Source 21 : +** Interrupt Source 22 : +** Interrupt Source 23 : +** Interrupt Source 24 : +** Interrupt Source 25 : PB[8] +** Interrupt Source 26 : PB[9] +** Interrupt Source 27 : PD[0] +** Interrupt Source 28 : PD[1] +** Interrupt Source 29 : +** Interrupt Source 30 : +** Non Maskable Interrupt Source 0 : +** Peripheral Type XOSC : +** Custom name : FXOSC +** Peripheral Type eMIOS : +** Custom name : eMIOS_0 +** eMIOS_0 : +** eMIOS0 ch0 type X : +** eMIOS0 ch0 type X : +** eMIOS_0: eMIOS0 ch0 type X : +** eMIOS0 ch10 type H : +** eMIOS0 ch10 type H : +** eMIOS_0: eMIOS0 ch10 type H : +** eMIOS0 ch11 type H : +** eMIOS0 ch11 type H : +** eMIOS_0: eMIOS0 ch11 type H : +** eMIOS0 ch12 type H : +** eMIOS0 ch12 type H : +** eMIOS_0: eMIOS0 ch12 type H : +** eMIOS0 ch13 type H : +** eMIOS0 ch13 type H : +** eMIOS_0: eMIOS0 ch13 type H : +** eMIOS0 ch14 type H : +** eMIOS0 ch14 type H : +** eMIOS_0: eMIOS0 ch14 type H : +** eMIOS0 ch15 type H : +** eMIOS0 ch15 type H : +** eMIOS_0: eMIOS0 ch15 type H : +** eMIOS0 ch16 type X : +** eMIOS0 ch16 type X : +** eMIOS_0: eMIOS0 ch16 type X : +** eMIOS0 ch17 type Y : +** eMIOS0 ch17 type Y : +** eMIOS_0: eMIOS0 ch17 type Y : +** eMIOS0 ch18 type Y : +** eMIOS0 ch18 type Y : +** eMIOS_0: eMIOS0 ch18 type Y : +** eMIOS0 ch19 type Y : +** eMIOS0 ch19 type Y : +** eMIOS_0: eMIOS0 ch19 type Y : +** eMIOS0 ch1 type G : +** eMIOS0 ch1 type G : +** eMIOS_0: eMIOS0 ch1 type G : +** eMIOS0 ch20 type Y : +** eMIOS0 ch20 type Y : +** eMIOS_0: eMIOS0 ch20 type Y : +** eMIOS0 ch21 type Y : +** eMIOS0 ch21 type Y : +** eMIOS_0: eMIOS0 ch21 type Y : +** eMIOS0 ch22 type X : +** eMIOS0 ch22 type X : +** eMIOS_0: eMIOS0 ch22 type X : +** eMIOS0 ch23 type X : +** eMIOS0 ch23 type X : +** eMIOS_0: eMIOS0 ch23 type X : +** eMIOS0 ch24 type X : +** eMIOS0 ch24 type X : +** eMIOS_0: eMIOS0 ch24 type X : +** eMIOS0 ch25 type Y : +** eMIOS0 ch25 type Y : +** eMIOS_0: eMIOS0 ch25 type Y : +** eMIOS0 ch26 type Y : +** eMIOS0 ch26 type Y : +** eMIOS_0: eMIOS0 ch26 type Y : +** eMIOS0 ch27 type Y : +** eMIOS0 ch27 type Y : +** eMIOS_0: eMIOS0 ch27 type Y : +** eMIOS0 ch28 type Y : +** eMIOS0 ch28 type Y : +** eMIOS_0: eMIOS0 ch28 type Y : +** eMIOS0 ch29 type Y : +** eMIOS0 ch29 type Y : +** eMIOS_0: eMIOS0 ch29 type Y : +** eMIOS0 ch2 type G : +** eMIOS0 ch2 type G : +** eMIOS_0: eMIOS0 ch2 type G : +** eMIOS0 ch30 type Y : +** eMIOS0 ch30 type Y : +** eMIOS_0: eMIOS0 ch30 type Y : +** eMIOS0 ch31 type Y : +** eMIOS0 ch31 type Y : +** eMIOS_0: eMIOS0 ch31 type Y : +** eMIOS0 ch3 type G : +** eMIOS0 ch3 type G : +** eMIOS_0: eMIOS0 ch3 type G : +** eMIOS0 ch4 type G : +** eMIOS0 ch4 type G : +** eMIOS_0: eMIOS0 ch4 type G : +** eMIOS0 ch5 type G : +** eMIOS0 ch5 type G : +** eMIOS_0: eMIOS0 ch5 type G : +** eMIOS0 ch6 type G : +** eMIOS0 ch6 type G : +** eMIOS_0: eMIOS0 ch6 type G : +** eMIOS0 ch7 type G : +** eMIOS0 ch7 type G : +** eMIOS_0: eMIOS0 ch7 type G : +** eMIOS0 ch8 type X : +** eMIOS0 ch8 type X : +** eMIOS_0: eMIOS0 ch8 type X : +** eMIOS0 ch9 type H : +** eMIOS0 ch9 type H : +** eMIOS_0: eMIOS0 ch9 type H : +** Custom name : eMIOS_1 +** eMIOS_1 : +** eMIOS1 ch0 type X : +** eMIOS1 ch0 type X : +** eMIOS_1: eMIOS1 ch0 type X : +** eMIOS1 ch10 type H : +** eMIOS1 ch10 type H : +** eMIOS_1: eMIOS1 ch10 type H : +** eMIOS1 ch11 type H : +** eMIOS1 ch11 type H : +** eMIOS_1: eMIOS1 ch11 type H : +** eMIOS1 ch12 type H : +** eMIOS1 ch12 type H : +** eMIOS_1: eMIOS1 ch12 type H : +** eMIOS1 ch13 type H : +** eMIOS1 ch13 type H : +** eMIOS_1: eMIOS1 ch13 type H : +** eMIOS1 ch14 type H : +** eMIOS1 ch14 type H : +** eMIOS_1: eMIOS1 ch14 type H : +** eMIOS1 ch15 type H : +** eMIOS1 ch15 type H : +** eMIOS_1: eMIOS1 ch15 type H : +** eMIOS1 ch16 type X : +** eMIOS1 ch16 type X : +** eMIOS_1: eMIOS1 ch16 type X : +** eMIOS1 ch17 type Y : +** eMIOS1 ch17 type Y : +** eMIOS_1: eMIOS1 ch17 type Y : +** eMIOS1 ch18 type Y : +** eMIOS1 ch18 type Y : +** eMIOS_1: eMIOS1 ch18 type Y : +** eMIOS1 ch19 type Y : +** eMIOS1 ch19 type Y : +** eMIOS_1: eMIOS1 ch19 type Y : +** eMIOS1 ch1 type H : +** eMIOS1 ch1 type H : +** eMIOS_1: eMIOS1 ch1 type H : +** eMIOS1 ch20 type Y : +** eMIOS1 ch20 type Y : +** eMIOS_1: eMIOS1 ch20 type Y : +** eMIOS1 ch21 type Y : +** eMIOS1 ch21 type Y : +** eMIOS_1: eMIOS1 ch21 type Y : +** eMIOS1 ch22 type X : +** eMIOS1 ch22 type X : +** eMIOS_1: eMIOS1 ch22 type X : +** eMIOS1 ch23 type X : +** eMIOS1 ch23 type X : +** eMIOS_1: eMIOS1 ch23 type X : +** eMIOS1 ch24 type X : +** eMIOS1 ch24 type X : +** eMIOS_1: eMIOS1 ch24 type X : +** eMIOS1 ch25 type Y : +** eMIOS1 ch25 type Y : +** eMIOS_1: eMIOS1 ch25 type Y : +** eMIOS1 ch26 type Y : +** eMIOS1 ch26 type Y : +** eMIOS_1: eMIOS1 ch26 type Y : +** eMIOS1 ch27 type Y : +** eMIOS1 ch27 type Y : +** eMIOS_1: eMIOS1 ch27 type Y : +** eMIOS1 ch28 type Y : +** eMIOS1 ch28 type Y : +** eMIOS_1: eMIOS1 ch28 type Y : +** eMIOS1 ch29 type Y : +** eMIOS1 ch29 type Y : +** eMIOS_1: eMIOS1 ch29 type Y : +** eMIOS1 ch2 type H : +** eMIOS1 ch2 type H : +** eMIOS_1: eMIOS1 ch2 type H : +** eMIOS1 ch30 type Y : +** eMIOS1 ch30 type Y : +** eMIOS_1: eMIOS1 ch30 type Y : +** eMIOS1 ch31 type Y : +** eMIOS1 ch31 type Y : +** eMIOS_1: eMIOS1 ch31 type Y : +** eMIOS1 ch3 type H : +** eMIOS1 ch3 type H : +** eMIOS_1: eMIOS1 ch3 type H : +** eMIOS1 ch4 type H : +** eMIOS1 ch4 type H : +** eMIOS_1: eMIOS1 ch4 type H : +** eMIOS1 ch5 type H : +** eMIOS1 ch5 type H : +** eMIOS_1: eMIOS1 ch5 type H : +** eMIOS1 ch6 type H : +** eMIOS1 ch6 type H : +** eMIOS_1: eMIOS1 ch6 type H : +** eMIOS1 ch7 type H : +** eMIOS1 ch7 type H : +** eMIOS_1: eMIOS1 ch7 type H : +** eMIOS1 ch8 type X : +** eMIOS1 ch8 type X : +** eMIOS_1: eMIOS1 ch8 type X : +** eMIOS1 ch9 type H : +** eMIOS1 ch9 type H : +** eMIOS_1: eMIOS1 ch9 type H : +** Custom name : eMIOS_2 +** eMIOS_2 : +** eMIOS2 ch0 type X : +** eMIOS2 ch0 type X : +** eMIOS_2: eMIOS2 ch0 type X : +** eMIOS2 ch10 type Y : +** eMIOS2 ch10 type Y : +** eMIOS_2: eMIOS2 ch10 type Y : +** eMIOS2 ch11 type Y : +** eMIOS2 ch11 type Y : +** eMIOS_2: eMIOS2 ch11 type Y : +** eMIOS2 ch12 type Y : +** eMIOS2 ch12 type Y : +** eMIOS_2: eMIOS2 ch12 type Y : +** eMIOS2 ch13 type Y : +** eMIOS2 ch13 type Y : +** eMIOS_2: eMIOS2 ch13 type Y : +** eMIOS2 ch14 type Y : +** eMIOS2 ch14 type Y : +** eMIOS_2: eMIOS2 ch14 type Y : +** eMIOS2 ch15 type Y : +** eMIOS2 ch15 type Y : +** eMIOS_2: eMIOS2 ch15 type Y : +** eMIOS2 ch16 type X : +** eMIOS2 ch16 type X : +** eMIOS_2: eMIOS2 ch16 type X : +** eMIOS2 ch17 type Y : +** eMIOS2 ch17 type Y : +** eMIOS_2: eMIOS2 ch17 type Y : +** eMIOS2 ch18 type Y : +** eMIOS2 ch18 type Y : +** eMIOS_2: eMIOS2 ch18 type Y : +** eMIOS2 ch19 type Y : +** eMIOS2 ch19 type Y : +** eMIOS_2: eMIOS2 ch19 type Y : +** eMIOS2 ch1 type Y : +** eMIOS2 ch1 type Y : +** eMIOS_2: eMIOS2 ch1 type Y : +** eMIOS2 ch20 type Y : +** eMIOS2 ch20 type Y : +** eMIOS_2: eMIOS2 ch20 type Y : +** eMIOS2 ch21 type Y : +** eMIOS2 ch21 type Y : +** eMIOS_2: eMIOS2 ch21 type Y : +** eMIOS2 ch22 type X : +** eMIOS2 ch22 type X : +** eMIOS_2: eMIOS2 ch22 type X : +** eMIOS2 ch23 type X : +** eMIOS2 ch23 type X : +** eMIOS_2: eMIOS2 ch23 type X : +** eMIOS2 ch24 type X : +** eMIOS2 ch24 type X : +** eMIOS_2: eMIOS2 ch24 type X : +** eMIOS2 ch25 type Y : +** eMIOS2 ch25 type Y : +** eMIOS_2: eMIOS2 ch25 type Y : +** eMIOS2 ch26 type Y : +** eMIOS2 ch26 type Y : +** eMIOS_2: eMIOS2 ch26 type Y : +** eMIOS2 ch29 type Y : +** eMIOS2 ch29 type Y : +** eMIOS_2: eMIOS2 ch29 type Y : +** eMIOS2 ch2 type Y : +** eMIOS2 ch2 type Y : +** eMIOS_2: eMIOS2 ch2 type Y : +** eMIOS2 ch30 type Y : +** eMIOS2 ch30 type Y : +** eMIOS_2: eMIOS2 ch30 type Y : +** eMIOS2 ch3 type Y : +** eMIOS2 ch3 type Y : +** eMIOS_2: eMIOS2 ch3 type Y : +** eMIOS2 ch4 type Y : +** eMIOS2 ch4 type Y : +** eMIOS_2: eMIOS2 ch4 type Y : +** eMIOS2 ch5 type Y : +** eMIOS2 ch5 type Y : +** eMIOS_2: eMIOS2 ch5 type Y : +** eMIOS2 ch6 type Y : +** eMIOS2 ch6 type Y : +** eMIOS_2: eMIOS2 ch6 type Y : +** eMIOS2 ch7 type Y : +** eMIOS2 ch7 type Y : +** eMIOS_2: eMIOS2 ch7 type Y : +** eMIOS2 ch8 type X : +** eMIOS2 ch8 type X : +** eMIOS_2: eMIOS2 ch8 type X : +** eMIOS2 ch9 type Y : +** eMIOS2 ch9 type Y : +** eMIOS_2: eMIOS2 ch9 type Y : +** Peripheral Type uSDHC : +** Custom name : uSDHC +** uSDHC : +** Card Clock : +** uSDHC: Card Clock : +** Command Line : +** uSDHC: Command Line : +** Data 0 Line : +** uSDHC: Data 0 Line : +** Data 1 Line : +** uSDHC: Data 1 Line : +** Data 2 Line : +** uSDHC: Data 2 Line : +** Data 3 Line : +** uSDHC: Data 3 Line : +** Data 4 Line : +** uSDHC: Data 4 Line : +** Data 5 Line : +** uSDHC: Data 5 Line : +** Data 6 Line : +** uSDHC: Data 6 Line : +** Data 7 Line : +** uSDHC: Data 7 Line : +** Reset : +** Write Protect : +** uSDHC: Write Protect : +** Non-peripheral pins : +** Electrical properties : +** Pin 1: PB[3] : +** Custom name, Signal name : PB[3] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 2: PC[9] : +** Custom name, Signal name : PC[9] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 3: PC[14] : +** Custom name, Signal name : PC[14] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 4: PC[15] : +** Custom name, Signal name : PC[15] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 5: PJ[4] : +** Custom name, Signal name : PJ[4] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 8: PH[15] : +** Custom name, Signal name : PH[15] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 9: PH[13] : +** Custom name, Signal name : PH[13] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 10: PH[14] : +** Custom name, Signal name : PH[14] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 11: PI[6] : +** Custom name, Signal name : PI[6] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 12: PI[7] : +** Custom name, Signal name : PI[7] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 13: PG[5] : +** Custom name, Signal name : PG[5] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 14: PG[4] : +** Custom name, Signal name : PG[4] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 15: PG[3] : +** Custom name, Signal name : PG[3] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 16: PG[2] : +** Custom name, Signal name : PG[2] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 17: PA[2] : +** Custom name, Signal name : PA[2] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 18: PE[0] : +** Custom name, Signal name : PE[0] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 19: PA[1] : +** Custom name, Signal name : PA[1] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 20: PE[1] : +** Custom name, Signal name : PE[1] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 21: PE[8] : +** Custom name, Signal name : PE[8] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 22: PE[9] : +** Custom name, Signal name : PE[9] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 23: PE[10] : +** Custom name, Signal name : PE[10] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 24: PA[0] : +** Custom name, Signal name : PA[0] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 25: PE[11] : +** Custom name, Signal name : PE[11] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 29: RESET : +** Custom name, Signal name : RESET +** Pin 31: VDD_LV : +** Custom name, Signal name : VDD_LV +** Pin 33: PG[9] : +** Custom name, Signal name : PG[9] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 34: PG[8] : +** Custom name, Signal name : PG[8] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 35: PC[11] : +** Custom name, Signal name : PC[11] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 36: PC[10] : +** Custom name, Signal name : PC[10] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 37: PG[7] : +** Custom name, Signal name : PG[7] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 38: PG[6] : +** Custom name, Signal name : PG[6] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 39: PB[0] : +** Custom name, Signal name : PB[0] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 40: PB[1] : +** Custom name, Signal name : PB[1] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 41: PF[9] : +** Custom name, Signal name : PF[9] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 42: PF[8] : +** Custom name, Signal name : PF[8] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 43: PF[12] : +** Custom name, Signal name : PF[12] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 44: PC[6] : +** Custom name, Signal name : PC[6] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 45: PC[7] : +** Custom name, Signal name : PC[7] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 46: PF[10] : +** Custom name, Signal name : PF[10] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 47: PF[11] : +** Custom name, Signal name : PF[11] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 48: PA[15] : +** Custom name, Signal name : PA[15] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 49: PF[13] : +** Custom name, Signal name : PF[13] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 50: PA[14] : +** Custom name, Signal name : PA[14] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 51: PA[4] : +** Custom name, Signal name : PA[4] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 52: PA[13] : +** Custom name, Signal name : PA[13] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 53: PA[12] : +** Custom name, Signal name : PA[12] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 56: XTAL : +** Custom name, Signal name : XTAL +** Pin 58: EXTAL : +** Custom name, Signal name : EXTAL +** Pin 60: PB[9] : +** Custom name, Signal name : PB[9] +** Analog Pad Control : +** Input Buffer Enable : +** Pull Select : +** Pullup Enable : +** Pin 61: PB[8] : +** Custom name, Signal name : PB[8] +** Analog Pad Control : +** Input Buffer Enable : +** Pull Select : +** Pullup Enable : +** Pin 62: PB[10] : +** Custom name, Signal name : PB[10] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 63: PF[0] : +** Custom name, Signal name : PF[0] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 64: PF[1] : +** Custom name, Signal name : PF[1] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 65: PF[2] : +** Custom name, Signal name : PF[2] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 66: PF[3] : +** Custom name, Signal name : PF[3] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 67: PF[4] : +** Custom name, Signal name : PF[4] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 68: PF[5] : +** Custom name, Signal name : PF[5] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 69: PF[6] : +** Custom name, Signal name : PF[6] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 70: PF[7] : +** Custom name, Signal name : PF[7] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 71: PJ[3] : +** Custom name, Signal name : PJ[3] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 72: PJ[2] : +** Custom name, Signal name : PJ[2] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 73: PJ[1] : +** Custom name, Signal name : PJ[1] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 74: PJ[0] : +** Custom name, Signal name : PJ[0] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 75: PI[15] : +** Custom name, Signal name : PI[15] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 76: PI[14] : +** Custom name, Signal name : PI[14] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 77: PD[0] : +** Custom name, Signal name : PD[0] +** Analog Pad Control : +** Input Buffer Enable : +** Pull Select : +** Pullup Enable : +** Pin 78: PD[1] : +** Custom name, Signal name : PD[1] +** Analog Pad Control : +** Input Buffer Enable : +** Pull Select : +** Pullup Enable : +** Pin 79: PD[2] : +** Custom name, Signal name : PD[2] +** Analog Pad Control : +** Input Buffer Enable : +** Pull Select : +** Pullup Enable : +** Pin 80: PD[3] : +** Custom name, Signal name : PD[3] +** Analog Pad Control : +** Input Buffer Enable : +** Pull Select : +** Pullup Enable : +** Pin 81: PD[4] : +** Custom name, Signal name : PD[4] +** Analog Pad Control : +** Input Buffer Enable : +** Pull Select : +** Pullup Enable : +** Pin 82: PD[5] : +** Custom name, Signal name : PD[5] +** Analog Pad Control : +** Input Buffer Enable : +** Pull Select : +** Pullup Enable : +** Pin 83: PD[6] : +** Custom name, Signal name : PD[6] +** Analog Pad Control : +** Input Buffer Enable : +** Pull Select : +** Pullup Enable : +** Pin 84: PD[7] : +** Custom name, Signal name : PD[7] +** Analog Pad Control : +** Input Buffer Enable : +** Pull Select : +** Pullup Enable : +** Pin 87: PD[8] : +** Custom name, Signal name : PD[8] +** Analog Pad Control : +** Input Buffer Enable : +** Pull Select : +** Pullup Enable : +** Pin 88: PB[4] : +** Custom name, Signal name : PB[4] +** Analog Pad Control : +** Input Buffer Enable : +** Pull Select : +** Pullup Enable : +** Pin 91: PB[5] : +** Custom name, Signal name : PB[5] +** Analog Pad Control : +** Input Buffer Enable : +** Pull Select : +** Pullup Enable : +** Pin 92: PB[6] : +** Custom name, Signal name : PB[6] +** Analog Pad Control : +** Input Buffer Enable : +** Pull Select : +** Pullup Enable : +** Pin 93: PB[7] : +** Custom name, Signal name : PB[7] +** Analog Pad Control : +** Input Buffer Enable : +** Pull Select : +** Pullup Enable : +** Pin 94: PD[9] : +** Custom name, Signal name : PD[9] +** Analog Pad Control : +** Input Buffer Enable : +** Pull Select : +** Pullup Enable : +** Pin 95: PD[10] : +** Custom name, Signal name : PD[10] +** Analog Pad Control : +** Input Buffer Enable : +** Pull Select : +** Pullup Enable : +** Pin 96: PB[11] : +** Custom name, Signal name : PB[11] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 98: VDD_HV_ADC1_REF : +** Custom name, Signal name : VDD_HV_ADC1_REF +** Pin 100: PD[12] : +** Custom name, Signal name : PD[12] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 101: PB[12] : +** Custom name, Signal name : PB[12] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 102: PD[13] : +** Custom name, Signal name : PD[13] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 103: PB[13] : +** Custom name, Signal name : PB[13] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 104: PD[14] : +** Custom name, Signal name : PD[14] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 105: PB[14] : +** Custom name, Signal name : PB[14] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 106: PD[15] : +** Custom name, Signal name : PD[15] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 107: PB[15] : +** Custom name, Signal name : PB[15] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 108: PI[8] : +** Custom name, Signal name : PI[8] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 111: PI[11] : +** Custom name, Signal name : PI[11] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 112: PI[12] : +** Custom name, Signal name : PI[12] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 113: PI[13] : +** Custom name, Signal name : PI[13] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 114: PA[3] : +** Custom name, Signal name : PA[3] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 115: PG[13] : +** Custom name, Signal name : PG[13] +** Slew Rate : Full drive strength without slew rate control +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 116: PG[12] : +** Custom name, Signal name : PG[12] +** Slew Rate : Full drive strength without slew rate control +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 117: PH[0] : +** Custom name, Signal name : PH[0] +** Slew Rate : Full drive strength without slew rate control +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 118: PH[1] : +** Custom name, Signal name : PH[1] +** Slew Rate : Full drive strength without slew rate control +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 119: PH[2] : +** Custom name, Signal name : PH[2] +** Slew Rate : Full drive strength without slew rate control +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 120: PH[3] : +** Custom name, Signal name : PH[3] +** Slew Rate : Full drive strength without slew rate control +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 121: PG[1] : +** Custom name, Signal name : PG[1] +** Slew Rate : Full drive strength without slew rate control +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 122: PG[0] : +** Custom name, Signal name : PG[0] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 125: PF[15] : +** Custom name, Signal name : PF[15] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 126: PF[14] : +** Custom name, Signal name : PF[14] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 127: PE[13] : +** Custom name, Signal name : PE[13] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 128: PA[7] : +** Custom name, Signal name : PA[7] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 129: PA[8] : +** Custom name, Signal name : PA[8] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 130: PA[9] : +** Custom name, Signal name : PA[9] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 131: PA[10] : +** Custom name, Signal name : PA[10] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 132: PA[11] : +** Custom name, Signal name : PA[11] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 133: PE[12] : +** Custom name, Signal name : PE[12] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Analog Pad Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 134: PG[14] : +** Custom name, Signal name : PG[14] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 135: PG[15] : +** Custom name, Signal name : PG[15] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 136: PE[14] : +** Custom name, Signal name : PE[14] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 137: PE[15] : +** Custom name, Signal name : PE[15] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 138: PG[10] : +** Custom name, Signal name : PG[10] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 139: PG[11] : +** Custom name, Signal name : PG[11] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 140: PH[11] : +** Custom name, Signal name : PH[11] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 141: PH[12] : +** Custom name, Signal name : PH[12] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 142: PI[5] : +** Custom name, Signal name : PI[5] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 143: PI[4] : +** Custom name, Signal name : PI[4] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 144: PC[3] : +** Custom name, Signal name : PC[3] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 145: PC[2] : +** Custom name, Signal name : PC[2] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 146: PA[5] : +** Custom name, Signal name : PA[5] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 147: PA[6] : +** Custom name, Signal name : PA[6] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 148: PH[10] : +** Custom name, Signal name : PH[10] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 149: PC[1] : +** Custom name, Signal name : PC[1] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 153: PORST : +** Custom name, Signal name : PORST +** Pin 154: PC[0] : +** Custom name, Signal name : PC[0] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 155: PH[9] : +** Custom name, Signal name : PH[9] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 156: PE[2] : +** Custom name, Signal name : PE[2] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 157: PE[3] : +** Custom name, Signal name : PE[3] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 158: PC[5] : +** Custom name, Signal name : PC[5] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 159: PC[4] : +** Custom name, Signal name : PC[4] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 160: PE[4] : +** Custom name, Signal name : PE[4] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 161: PE[5] : +** Custom name, Signal name : PE[5] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 162: PH[4] : +** Custom name, Signal name : PH[4] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 163: PH[5] : +** Custom name, Signal name : PH[5] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 164: PH[6] : +** Custom name, Signal name : PH[6] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 165: PH[7] : +** Custom name, Signal name : PH[7] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 166: PH[8] : +** Custom name, Signal name : PH[8] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 167: PE[6] : +** Custom name, Signal name : PE[6] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 168: PE[7] : +** Custom name, Signal name : PE[7] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 169: PI[3] : +** Custom name, Signal name : PI[3] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 170: PI[2] : +** Custom name, Signal name : PI[2] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 171: PI[1] : +** Custom name, Signal name : PI[1] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 172: PI[0] : +** Custom name, Signal name : PI[0] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 173: PC[12] : +** Custom name, Signal name : PC[12] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Interrupt Edge : +** Pin 174: PC[13] : +** Custom name, Signal name : PC[13] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 175: PC[8] : +** Custom name, Signal name : PC[8] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Pin 176: PB[2] : +** Custom name, Signal name : PB[2] +** Slew Rate : +** Output Buffer Enable : +** Open Drain Enable : +** Safe Mode Control : +** Input Buffer Enable : +** Hysteresis Enable : +** Pull Select : +** Pullup Enable : +** Out Mux Field : +** Initial Value Field : +** Settings : +** PinSetting Configuration Generation Settings : +** UtilizeResetValuesCondGroup : Only if property present +** Generate configured Pins only : yes +** Contents : +** PINS_DRV_Init - status_t PINS_DRV_Init(uint32_t pinCount,const pin_settings_config_t config[]); +** PINS_DRV_SetPullSel - void PINS_DRV_SetPullSel(PORT_Type * const base,uint16_t... +** PINS_DRV_SetOutputBuffer - void PINS_DRV_SetOutputBuffer(PORT_Type * const base,uint16_t pin,bool... +** PINS_DRV_SetInputBuffer - void PINS_DRV_SetInputBuffer(PORT_Type * const base,uint16_t pin,bool... +** PINS_DRV_ConfigIntFilterClock - void PINS_DRV_ConfigIntFilterClock(uint8_t prescaler); +** PINS_DRV_SetExInt - void PINS_DRV_SetExInt(siul2_interrupt_config_t intConfig); +** PINS_DRV_ClearPinExIntFlag - void PINS_DRV_ClearPinExIntFlag(uint32_t eirqPinIdx); +** PINS_DRV_GetPinExIntFlag - bool PINS_DRV_GetPinExIntFlag(uint32_t eirqPinIdx); +** PINS_DRV_ClearExIntFlag - void PINS_DRV_ClearExIntFlag(); +** PINS_DRV_GetExIntFlag - uint32_t PINS_DRV_GetExIntFlag(); +** PINS_DRV_WritePin - void PINS_DRV_WritePin(GPIO_Type * const base,pins_channel_type_t... +** PINS_DRV_WritePins - void PINS_DRV_WritePins(GPIO_Type * const base,pins_channel_type_t pins); +** PINS_DRV_GetPinsOutput - pins_channel_type_t PINS_DRV_GetPinsOutput(const GPIO_Type * const base); +** PINS_DRV_SetPins - void PINS_DRV_SetPins(GPIO_Type * const base,pins_channel_type_t pins); +** PINS_DRV_ClearPins - void PINS_DRV_ClearPins(GPIO_Type * const base,pins_channel_type_t pins); +** PINS_DRV_TogglePins - void PINS_DRV_TogglePins(GPIO_Type * const base,pins_channel_type_t pins); +** PINS_DRV_ReadPins - pins_channel_type_t PINS_DRV_ReadPins(const GPIO_Type * const base); +** +** Copyright 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All Rights Reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** ###################################################################*/ +/*! +** @file pin_mux.h +** @version 1.4 +** @brief +** +*/ +/*! +** @addtogroup pin_mux_module pin_mux module documentation +** @{ +*/ + +#ifndef pin_mux_H +#define pin_mux_H + +/* MODULE pin_mux. */ +#include "pins_driver.h" + +/*! @brief User number of configured pins */ +#define NUM_OF_CONFIGURED_PINS 38 + +/*! @brief User configuration structure */ +extern pin_settings_config_t g_pin_mux_InitConfigArr[NUM_OF_CONFIGURED_PINS]; + +/* END pin_mux. */ +#endif /* #ifndef pin_mux_H */ +/*! +** @} +*/ +/* +** ################################################################### +** +** This file was created by Processor Expert 10.1 [05.21] +** for the NXP C55 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/flexray_adapter/flexray_adapter/ProcessorExpert.pe b/flexray_adapter/flexray_adapter/ProcessorExpert.pe new file mode 100644 index 00000000000000..6a51465c46d3cc --- /dev/null +++ b/flexray_adapter/flexray_adapter/ProcessorExpert.pe @@ -0,0 +1,52672 @@ + + +
+ flexray_adapter + B19337 + 164 + 2017-03-07 + Eclipse IDE + 1.12.2.RT7_b1743-0713 +
+ + main + Sources + Generated_Code + Documentation + + Project_Settings + Generated_Code + + 3 + 3 + 3 + true + false + true + 0 + false + false + true + false + true + 129 + true + false + true + CLASSIC + true + true + false + + LINKED + ${eclipse_home}../S32DS/S32_SDK_MPC574xx_RTM_1.0.0 + + SDK_MPC574x_06 + SDK_MPC574x_06 + SDK_MPC574x_06 + + + + Referenced_Components + 5 + Beans + true + + + file:/${ProcessorExpert_loc}/../../S32DS/S32_SDK_MPC574xx_RTM_1.0.0/tools/pex/Repositories/SDK_MPC574x_06_Repository + MPC5748G_176 + Cpu + 2 + true + ALWAYS_WRITE + CPU_CHIP2 + + +