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Add v128.load32_zero and v128.load64_zero SIMD instructions (#119)
* Add v128.load32_zero and v128.load64_zero SIMD instructions * Update formatting
1 parent 51c78e5 commit bdbb2d4

5 files changed

Lines changed: 16 additions & 1 deletion

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crates/wasmparser/src/binary_reader.rs

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@@ -1728,6 +1728,12 @@ impl<'a> BinaryReader<'a> {
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0xf9 => Operator::I32x4TruncSatF32x4U,
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0xfa => Operator::F32x4ConvertI32x4S,
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0xfb => Operator::F32x4ConvertI32x4U,
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0xfc => Operator::V128Load32Zero {
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memarg: self.read_memarg_of_align(2)?,
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},
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0xfd => Operator::V128Load64Zero {
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memarg: self.read_memarg_of_align(3)?,
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},
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_ => {
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return Err(BinaryReaderError::new(
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format!("Unknown 0xfd subopcode: 0x{:x}", code),

crates/wasmparser/src/operators_validator.rs

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@@ -1593,13 +1593,14 @@ impl OperatorValidator {
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self.pop_operand(Some(ty))?;
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self.push_operand(Type::V128)?;
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}
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Operator::V128Load32Splat { memarg } => {
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Operator::V128Load32Splat { memarg } | Operator::V128Load32Zero { memarg } => {
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self.check_simd_enabled()?;
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let ty = self.check_memarg(memarg, 2, resources)?;
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self.pop_operand(Some(ty))?;
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self.push_operand(Type::V128)?;
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}
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Operator::V128Load64Splat { memarg }
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| Operator::V128Load64Zero { memarg }
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| Operator::V128Load8x8S { memarg }
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| Operator::V128Load8x8U { memarg }
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| Operator::V128Load16x4S { memarg }

crates/wasmparser/src/primitives.rs

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@@ -781,7 +781,9 @@ pub enum Operator<'a> {
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V128Load8Splat { memarg: MemoryImmediate },
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V128Load16Splat { memarg: MemoryImmediate },
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V128Load32Splat { memarg: MemoryImmediate },
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V128Load32Zero { memarg: MemoryImmediate },
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V128Load64Splat { memarg: MemoryImmediate },
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V128Load64Zero { memarg: MemoryImmediate },
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I8x16NarrowI16x8S,
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I8x16NarrowI16x8U,
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I16x8NarrowI32x4S,

crates/wasmprinter/src/lib.rs

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@@ -1271,6 +1271,9 @@ impl Printer {
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V128Load32Splat { memarg } => self.mem_instr("v128.load32_splat", memarg, 4)?,
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V128Load64Splat { memarg } => self.mem_instr("v128.load64_splat", memarg, 8)?,
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V128Load32Zero { memarg } => self.mem_instr("v128.load32_zero", memarg, 4)?,
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V128Load64Zero { memarg } => self.mem_instr("v128.load64_zero", memarg, 8)?,
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I8x16NarrowI16x8S => self.result.push_str("i8x16.narrow_i16x8_s"),
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I8x16NarrowI16x8U => self.result.push_str("i8x16.narrow_i16x8_u"),
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I16x8NarrowI32x4S => self.result.push_str("i16x8.narrow_i32x4_s"),

crates/wast/src/ast/expr.rs

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Original file line numberDiff line numberDiff line change
@@ -993,6 +993,9 @@ instructions! {
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F32x4ConvertI32x4S : [0xfd, 0xfa] : "f32x4.convert_i32x4_s",
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F32x4ConvertI32x4U : [0xfd, 0xfb] : "f32x4.convert_i32x4_u",
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V128Load32Zero : [0xfd, 0xfc] : "v128.load32_zero",
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V128Load64Zero : [0xfd, 0xfd] : "v128.load64_zero",
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// Exception handling proposal
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Try(BlockType<'a>) : [0x06] : "try",
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Catch : [0x07] : "catch",

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