[RFC] Integration of sparse-ternary-fma for accelerated ternary operations

Pull Request Type: Request for Comment (RFC)
Target Repository: microsoft/BitNet
Source Branch: HyperFoldUK:main
Target Branch: microsoft:main
Author: HyperFoldUK maurice.wilson@hyperfold-technologies.com

Purpose

This RFC proposes the integration of the sparse-ternary-fma library into BitNet to significantly accelerate ternary matrix operations through optimized 2-bit encoding and SIMD instructions (AVX2/AVX-512).

Background & Principle

BitNet's 1.58-bit quantization represents weights as ternary values {-1, 0, +1}, enabling extreme model compression while maintaining competitive accuracy. However, the current implementation faces efficiency constraints:

Sparse representation overhead: Standard 8-bit storage wastes 6 bits per ternary value
Branch-heavy operations: Conditional logic for ternary arithmetic disrupts CPU pipelines
Underutilized SIMD: Limited vectorization of ternary operations on modern hardware

The sparse-ternary-fma library addresses these limitations through:

2-bit encoding: 4× memory density (4 trits per byte vs 1 trit per byte)
Branchless operations: Pure bitwise logic eliminates pipeline stalls
SIMD acceleration: AVX2/AVX-512 implementations process 8-16 elements in parallel
Zero-aware sparsity: Skips zero-valued weights automatically

Why This Matters

Ternary quantization is fundamentally different from traditional quantization. The presence of explicit zeros creates opportunities for sparsity-aware computation that standard quantization approaches cannot exploit. By using 2-bit encoding and SIMD operations, we can:

Reduce memory bandwidth: 4× reduction in data movement
Improve cache efficiency: More weights fit in L1/L2 cache
Enable parallel processing: Process 8-16 trits simultaneously with SIMD
Eliminate branching: Branchless operations improve pipeline efficiency

This Implementation

This fork demonstrates a clean integration:

Architecture

┌─────────────────────────────────────────────────────────────┐
│ Layer 4: Build System (CMakeLists.txt)                     │
│ - BITNET_USE_STFMA option                                  │
│ - GGML_BITNET_STFMA_THRESHOLD configuration                │
└─────────────────────────────────────────────────────────────┘
                              │
┌─────────────────────────────────────────────────────────────┐
│ Layer 3: BitNet API Integration (ggml-bitnet-mad.cpp)      │
│ - Automatic dispatch in ggml_vec_dot_i2_i8_s()             │
│ - Threshold-based selection                                │
└─────────────────────────────────────────────────────────────┘
                              │
┌─────────────────────────────────────────────────────────────┐
│ Layer 2: BitNet Adapter (ggml-bitnet-stfma.h/cpp)          │
│ - Encoding conversion (BitNet ↔ sparse-ternary-fma)        │
│ - Type conversion (int8 ↔ int32)                           │
│ - Thread-local buffer management                           │
│ - int32 variants of sparse ternary FMA                     │
└─────────────────────────────────────────────────────────────┘
                              │
┌─────────────────────────────────────────────────────────────┐
│ Layer 1: Core sparse-ternary-fma Library (3rdparty/)       │
│ - 2-bit encoding/decoding                                  │
│ - Scalar, AVX2, AVX-512 implementations                    │
│ - Sparse index format support                              │
└─────────────────────────────────────────────────────────────┘

Key Optimizations

1. Branchless Encoding Conversion

Replaces loop+switch with pure bitwise operations:

/**
 * BitNet pairs:  00 (-1), 01 (0), 10 (+1), 11 (invalid)
 * STFMA pairs:   10 (-1), 00 (0), 01 (+1), 11 (invalid)
 *
 * Formula:
 *   out_low  = in_high
 *   out_high = ~(in_high XOR in_low)
 */
uint8_t convert_bitnet_to_stfma_byte(uint8_t b) {
    uint8_t low_bits = b & 0x55;
    uint8_t high_bits = b & 0xAA;
    uint8_t out_low = (high_bits >> 1);
    uint8_t high_bits_shifted = (high_bits >> 1);
    uint8_t xor_result = high_bits_shifted ^ low_bits;
    uint8_t out_high = (~xor_result) & 0x55;
    out_high = out_high << 1;
    return out_high | out_low;
}

Impact: Zero branches, processes 4 trits in parallel, ~5 assembly instructions

2. SIMD Trit Unpacking

Eliminates stack round-trip by unpacking directly in registers:

// Before: Stack round-trip
int32_t trits[16];
for (int j = 0; j < 16; j++) {
    trits[j] = (trit_packed >> (j * 2)) & 0b11;
}
__m512i trit_vec = _mm512_loadu_si512(trits);  // Memory load!

// After: Direct SIMD unpacking
__m512i packed_vec = _mm512_set1_epi32(trit_packed);
__m512i shift_amounts = _mm512_setr_epi32(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30);
__m512i shifted = _mm512_srlv_epi32(packed_vec, shift_amounts);
__m512i mask_2bits = _mm512_set1_epi32(0b11);
__m512i trit_vec = _mm512_and_si512(shifted, mask_2bits);

Impact: Eliminates 16 scalar operations + 1 memory load, stays in registers

3. Thread-Local Buffer Pooling

static thread_local struct stfma_thread_buffers {
    uint8_t* encoding_buffer;
    int32_t* int32_buffer;
    int32_t* accumulator_buffer;
    size_t buffer_size;
} tl_buffers;

Impact: Zero allocations in hot path after warmup

4. Threshold-Based Dispatch

void ggml_vec_dot_i2_i8_s(int n, float* s, const void* vx, const void* vy) {
#ifdef BITNET_USE_STFMA
    if (n >= GGML_BITNET_STFMA_THRESHOLD) {
        ggml_vec_dot_i2_i8_stfma(n, s, vx, vy);
        return;
    }
#endif
    // Fall back to original implementation
    ggml_vec_dot_i2_i8_s_original(n, s, vx, vy);
}

Impact: Automatic selection based on operation size

Small ops (<1024): Original implementation (lower overhead)
Large ops (≥1024): sparse-ternary-fma (higher throughput)

Integration Points

Modified Files:

src/ggml-bitnet-mad.cpp - Added automatic dispatch logic

New Files:

include/ggml-bitnet-stfma.h - Adapter layer API
src/ggml-bitnet-stfma.cpp - Adapter layer implementation
3rdparty/sparse-ternary-fma/ - Vendored library (Apache 2.0 licensed)

Build System:

CMakeLists.txt - Added sparse-ternary-fma configuration
src/CMakeLists.txt - Added adapter source files

Performance

Based on sparse-ternary-fma benchmarks on Intel Xeon with AVX-512:

Metric	Improvement
Throughput	2.38× faster
Latency (sparse)	26.12× faster
Memory density	4× denser (2-bit vs 8-bit)
Cache utilization	Significantly improved

Benchmark Details

Dense operations (N=4096):
  Scalar:    1.23 GFLOPS
  AVX2:      3.45 GFLOPS
  AVX-512:   8.21 GFLOPS (2.38× vs scalar)

Sparse operations (80% zeros, N=4096):
  Scalar:    0.89 GFLOPS
  AVX2:      2.67 GFLOPS
  AVX-512:   23.25 GFLOPS (26.12× vs scalar)

Memory

Encoding Efficiency

Representation	Bits per Trit	Trits per Byte	Memory for 1M Trits
int8 (current)	8	1	1 MB
2-bit (STFMA)	2	4	256 KB
Savings	-75%	4×	768 KB saved

Runtime Overhead

Thread-local buffers: Allocated once per thread, reused across calls
Conversion cost: ~5 assembly instructions per byte (branchless)
Type conversion: Vectorized int8→int32 conversion using SIMD

Memory Access Pattern

Traditional approach:
  Load 8 bytes (8 trits) → Process → Store

sparse-ternary-fma:
  Load 2 bytes (8 trits) → Unpack in registers → Process → Store
  
Result: 4× reduction in memory bandwidth

Design

Backward Compatibility

✅ No breaking changes

Falls back to original implementation for small operations
Can be completely disabled: -DBITNET_USE_STFMA=OFF
No changes to public API
Existing models work without modification

Configurability

CMake Options:

# Enable/disable integration (default: ON)
-DBITNET_USE_STFMA=ON

# Set dispatch threshold (default: 1024)
-DGGML_BITNET_STFMA_THRESHOLD=2048

Runtime Behavior:

Operations with n < threshold: Use original implementation
Operations with n >= threshold: Use sparse-ternary-fma
Automatic hardware detection (AVX-512 > AVX2 > Scalar)

Testing

Test Suite Location: tests/stfma_integration/

Coverage:

Branchless conversion - All 256 possible byte encodings verified
AVX-512 unpacking - SIMD unpacking correctness
End-to-end integration - Full pipeline verification
Pattern analysis - Bit pattern transformation validation

Test Results:

✓ Branchless conversion: 256/256 passed
✓ AVX-512 unpacking: All patterns correct
✓ Integration test: 6/6 tests passed

Code Quality

Zero compiler warnings with -Wall -Wextra -Wpedantic
Verified with AddressSanitizer (no memory leaks)
Consistent coding style matching BitNet conventions
Comprehensive inline documentation

Full Documentation

Complete technical documentation is available in:

STFMA_INTEGRATION_README.md - Integration guide
tests/stfma_integration/README.md - Test suite documentation
3rdparty/sparse-ternary-fma/TECHNICAL.md - Library deep-dive

We are seeking feedback from the maintainers and community on:

1. The technical approach and integration design

Questions:

Is the adapter layer architecture appropriate, or would you prefer a different approach?
Should encoding conversion be optimized further (e.g., using lookup tables)?
Are there better integration points in the BitNet codebase?
Would you prefer the integration to be more tightly coupled or remain as a separate layer?

Trade-offs:

Current approach: Clean separation, easy to disable, minimal code changes
Alternative: Native encoding change (more invasive but eliminates conversion overhead)

2. Performance characteristics on diverse hardware

Needed benchmarks:

Real-world inference latency on various model sizes
Performance on AMD vs Intel processors
AVX2-only systems (no AVX-512)
ARM platforms (currently unsupported)
Impact on end-to-end throughput vs isolated operations

Questions:

What threshold values work best for different hardware?
Is the conversion overhead acceptable for your use cases?
Are there specific workloads where this performs worse?

3. The potential path to upstream adoption

Integration options:

Option A: Optional Feature (Current Approach)

✅ Minimal risk, easy to disable
✅ No breaking changes
❌ Conversion overhead remains

Option B: Native Encoding Change

✅ Eliminates conversion overhead
✅ Maximum performance
❌ Breaking change, requires model re-quantization

Option C: Hybrid Approach

✅ Support both encodings
✅ Gradual migration path
❌ Increased complexity

Questions:

Which integration option aligns with BitNet's roadmap?
What additional testing/validation is needed for production use?
Are there licensing or dependency concerns with vendoring sparse-ternary-fma?
Should this target specific hardware (e.g., AVX-512 only) or be broadly available?

The code is complete, tested, and ready for review.

We believe this addresses a fundamental efficiency ceiling for ternary computation. By leveraging 2-bit encoding and SIMD acceleration, we can unlock significant performance gains for BitNet models while maintaining full backward compatibility.

What's Included

✅ Complete implementation with all optimizations
✅ Comprehensive test suite with 100% pass rate
✅ Full documentation including integration guide
✅ Backward compatibility with existing code
✅ Configurable behavior via CMake options
✅ Clean commit history with detailed messages

Commit Summary

Integrate sparse-ternary-fma for optimized ternary matrix operations
- Add sparse-ternary-fma library as 3rdparty dependency
- Create adapter layer for BitNet integration
- Implement automatic dispatch with configurable threshold
Optimize encoding conversion with branchless bitwise logic
- Replace loop+switch with XOR-based formula
- Process 4 trits in parallel
- Eliminate branch misprediction penalties
Optimize AVX2/AVX-512 trit unpacking to eliminate stack round-trip
- Use variable shift instructions for direct unpacking
- Keep all operations in registers
- Reduce instruction count significantly
Organize test files and artifacts into tests/stfma_integration directory
- Add comprehensive test suite
- Include verification programs
- Document all tests

All commits are authored by HyperFoldUK maurice.wilson@hyperfold-technologies.com

Related Work

sparse-ternary-fma library: https://github.com/HyperFoldUK/sparse-ternary-fma
Technical deep-dive: https://github.com/HyperFoldUK/sparse-ternary-fma/blob/main/TECHNICAL.md
Benchmark results: https://github.com/HyperFoldUK/sparse-ternary-fma#performance

How to Review

Quick Start

Clone the fork:

git clone https://github.com/HyperFoldUK/BitNet.git
cd BitNet

Build with integration:

mkdir build && cd build
cmake ..
make -j$(nproc)

Run tests:

cd tests/stfma_integration
g++ -o test_final test_final.cpp -O3 && ./test_final
g++ -o test_avx512_unpack test_avx512_unpack.cpp -mavx512f -O3 && ./test_avx512_unpack

Detailed Review

Architecture: Review STFMA_INTEGRATION_README.md for design overview
Implementation: Check src/ggml-bitnet-stfma.cpp for adapter layer
Integration: Review src/ggml-bitnet-mad.cpp for dispatch logic
Tests: Examine tests/stfma_integration/ for verification

Contact

For questions or discussions:

GitHub Issues: https://github.com/HyperFoldUK/BitNet/issues
Email: maurice.wilson@hyperfold-technologies.com

We look forward to your feedback and are happy to make adjustments based on maintainer preferences.

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[RFC] Integration of sparse-ternary-fma for accelerated ternary operations

Purpose

Background & Principle

Why This Matters

This Implementation

Architecture

Key Optimizations

1. Branchless Encoding Conversion

2. SIMD Trit Unpacking

3. Thread-Local Buffer Pooling

4. Threshold-Based Dispatch

Integration Points

Performance

Benchmark Details

Memory

Encoding Efficiency

Runtime Overhead

Memory Access Pattern

Design

Backward Compatibility

Configurability

Testing

Code Quality

Full Documentation

We are seeking feedback from the maintainers and community on:

1. The technical approach and integration design

2. Performance characteristics on diverse hardware

3. The potential path to upstream adoption

The code is complete, tested, and ready for review.

What's Included

Commit Summary

Related Work

How to Review

Quick Start

Detailed Review

Contact

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RFC_PULL_REQUEST.md

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RFC_PULL_REQUEST.md

File metadata and controls

[RFC] Integration of sparse-ternary-fma for accelerated ternary operations

Purpose

Background & Principle

Why This Matters

This Implementation

Architecture

Key Optimizations

1. Branchless Encoding Conversion

2. SIMD Trit Unpacking

3. Thread-Local Buffer Pooling

4. Threshold-Based Dispatch

Integration Points

Performance

Benchmark Details

Memory

Encoding Efficiency

Runtime Overhead

Memory Access Pattern

Design

Backward Compatibility

Configurability

Testing

Code Quality

Full Documentation

We are seeking feedback from the maintainers and community on:

1. The technical approach and integration design

2. Performance characteristics on diverse hardware

3. The potential path to upstream adoption

The code is complete, tested, and ready for review.

What's Included

Commit Summary

Related Work

How to Review

Quick Start

Detailed Review

Contact